[PATCH 3/3] arm64: dts: freescale: imx{91,93}-phycore-som: Improve USDHC signals
Primoz Fiser
primoz.fiser at norik.com
Wed May 6 23:20:58 PDT 2026
From: Christoph Stoidner <c.stoidner at phytec.de>
Apply improved drive-strength values and pull-up/down configurations as
devised from hardware measurements to improve signal quality on PHYTEC
phyCORE-i.MX 91/93 SoM based boards. Also improve eMMC HS400 mode by
setting property "fsl,strobe-dll-delay-target" which shifts the strobe
DLL sampling window to the optimal position.
Signed-off-by: Christoph Stoidner <c.stoidner at phytec.de>
Signed-off-by: Primoz Fiser <primoz.fiser at norik.com>
---
.../boot/dts/freescale/imx91-phyboard-segin.dts | 6 +++---
.../arm64/boot/dts/freescale/imx91-phycore-som.dtsi | 13 +++++++------
.../boot/dts/freescale/imx93-phyboard-nash.dts | 8 ++++----
.../boot/dts/freescale/imx93-phyboard-segin.dts | 6 +++---
.../arm64/boot/dts/freescale/imx93-phycore-som.dtsi | 13 +++++++------
5 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
index 7b18a58024f5..aec83da87c4e 100644
--- a/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-phyboard-segin.dts
@@ -309,7 +309,7 @@ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x118e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1386
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
@@ -321,7 +321,7 @@ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x159e
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
@@ -333,7 +333,7 @@ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
- MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x118e
MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
diff --git a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
index 8038d92da2aa..d9397080fe48 100644
--- a/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi
@@ -194,6 +194,7 @@ &usdhc1 {
bus-width = <8>;
non-removable;
no-1-8-v;
+ fsl,strobe-dll-delay-target = <1>;
status = "okay";
};
@@ -252,7 +253,7 @@ MX91_PAD_ENET2_RD3__GPIO4_IO27 0x31e
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x179e
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x119e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1386
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1386
@@ -262,13 +263,13 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1386
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1386
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1386
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1386
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x139e
@@ -278,13 +279,13 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x139e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x139e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x139e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x139e
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
- MX91_PAD_SD1_CLK__USDHC1_CLK 0x17be
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX91_PAD_SD1_CMD__USDHC1_CMD 0x139e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x139e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13be
@@ -294,7 +295,7 @@ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13be
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13be
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13be
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13be
- MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
index eac389ed30f3..a7bd490b042b 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-nash.dts
@@ -339,8 +339,8 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
- MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000178e
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
+ MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001386
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001386
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001386
@@ -352,7 +352,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
@@ -365,7 +365,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
diff --git a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
index a982606de1ee..291b409b159f 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-phyboard-segin.dts
@@ -310,7 +310,7 @@ MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_default: usdhc2grp {
fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
@@ -323,7 +323,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x159e
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x119e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
@@ -336,7 +336,7 @@ MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
- MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX93_PAD_SD2_CLK__USDHC2_CLK 0x118e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
diff --git a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
index a624aed48efe..4276140afb5c 100644
--- a/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-phycore-som.dtsi
@@ -196,6 +196,7 @@ &usdhc1 {
bus-width = <8>;
non-removable;
no-1-8-v;
+ fsl,strobe-dll-delay-target = <1>;
status = "okay";
};
@@ -255,7 +256,7 @@ MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x179e
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x119e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001386
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001386
@@ -265,14 +266,14 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001386
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001386
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001386
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001386
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e
@@ -282,14 +283,14 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
- MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
+ MX93_PAD_SD1_CLK__USDHC1_CLK 0x11be
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be
@@ -299,7 +300,7 @@ MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be
- MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e
+ MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x159e
>;
};
--
2.34.1
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