[PATCH v3 2/3] dt-bindings: gpio: Add EIO GPIO compatible to gpio-zynq
Rob Herring
robh at kernel.org
Tue May 5 12:46:23 PDT 2026
On Tue, Apr 21, 2026 at 04:13:57PM +0530, Shubhrajyoti Datta wrote:
> EIO (Extended IO) GPIO is a Xilinx IP block that exposes
> multiplexed I/O pins through an EIO interface.
>
> The EIO GPIO block has 2 banks with 26 GPIOs each (52 total).
> The GPIO width cannot be determined from the hardware registers,
> the driver relies on the compatible string to select the correct
> bank/pin configuration. A new compatible is therefore required.
>
> The block is currently present on xa2ve3288 silicon.
> The compatible string uses version 1.0 matching the IP core version.
>
> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta at amd.com>
> ---
>
> Changes in v3:
> - Update the commit message
>
> Changes in v2:
> - Add description of EIO block
>
> .../devicetree/bindings/gpio/gpio-zynq.yaml | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> index 30a7f836c341..1ca067217509 100644
> --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
> @@ -12,6 +12,7 @@ maintainers:
> properties:
> compatible:
> enum:
> + - xlnx,eio-gpio-1.0
> - xlnx,pmc-gpio-1.0
> - xlnx,versal-gpio-1.0
> - xlnx,zynq-gpio-1.0
> @@ -30,7 +31,7 @@ properties:
>
> gpio-line-names:
> description: strings describing the names of each gpio line
> - minItems: 58
> + minItems: 52
> maxItems: 174
>
> interrupt-controller: true
> @@ -89,6 +90,17 @@ allOf:
> minItems: 116
> maxItems: 116
>
> + - if:
> + properties:
> + compatible:
> + enum:
> + - xlnx,eio-gpio-1.0
> + then:
> + properties:
> + gpio-line-names:
> + minItems: 52
The min is already 52, so you can drop this. With that,
Acked-by: Rob Herring (Arm) <robh at kernel.org>
> + maxItems: 52
> +
> required:
> - compatible
> - reg
> --
> 2.34.1
>
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