[PATCH] arm64: dts: ti: k3-j721e-main: Update delay select values for MMC1/2 subsystems

[Moteen Shah]

Hey Romain,

Thanks for the patch

On 19/02/26 02:08, Romain Naour wrote:
> The previous SPRSP36J datasheet recommends to set ti,otap-del-sel-sd-hs
> value to 0 for MMC1 and MMC2 interfaces. These values were updated in
> kernel 6.5. As a result we have some occasional regression with ultra
> high speed DDR50 SDXC cards while mounting the rootfs:

This error shouldn't be limited to just DDR50, were you seeing similar 
behavior with other speed modes?
>
>    mmc1: error -110 whilst initialising SD card
>
> A similar issue may occur with u-boot after a reboot while
> initialising the SD card:
>
>    mmc_init: -110, time 67
>
> Update the delay values for legacy and high speed modes, based on
> the latest revised datasheet SPRSP36K released in April 2024 [1].
>
>    (MMC1/2 - SD/SDIO Interface): Updated/Changed the
>    "OTAPDLYENA, DELAY ENABLE" and "OTAPDLYSEL, DELAY VALUE" for the
>    Default Speed and High Speed modes from "0x0" to "0x1"
>
> [1] Table 6-86. MMC1/2 DLL Delay Mapping for All Timing Modes, in
> https://www.ti.com/lit/ds/symlink/tda4vm.pdf,
> (SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024)
>
> Cc: stable at vger.kernel.org # 6.5+
> Fixes: af398252d68e ("arm64: dts: ti: k3-j721e-main: Update delay select values for MMC subsystems")
> Signed-off-by: Romain Naour <romain.naour at smile.fr>
> ---
>   arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index d5fd30a01032..418e6010ef1f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -1643,8 +1643,8 @@ main_sdhci1: mmc at 4fb0000 {
>   		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
>   		assigned-clocks = <&k3_clks 92 0>;
>   		assigned-clock-parents = <&k3_clks 92 1>;
> -		ti,otap-del-sel-legacy = <0x0>;
> -		ti,otap-del-sel-sd-hs = <0x0>;
> +		ti,otap-del-sel-legacy = <0x1>;
> +		ti,otap-del-sel-sd-hs = <0x1>;
>   		ti,otap-del-sel-sdr12 = <0xf>;
>   		ti,otap-del-sel-sdr25 = <0xf>;
>   		ti,otap-del-sel-sdr50 = <0xc>;
> @@ -1671,8 +1671,8 @@ main_sdhci2: mmc at 4f98000 {
>   		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
>   		assigned-clocks = <&k3_clks 93 0>;
>   		assigned-clock-parents = <&k3_clks 93 1>;
> -		ti,otap-del-sel-legacy = <0x0>;
> -		ti,otap-del-sel-sd-hs = <0x0>;
> +		ti,otap-del-sel-legacy = <0x1>;
> +		ti,otap-del-sel-sd-hs = <0x1>;
>   		ti,otap-del-sel-sdr12 = <0xf>;
>   		ti,otap-del-sel-sdr25 = <0xf>;
>   		ti,otap-del-sel-sdr50 = <0xc>;


Reviewed-by: Moteen Shah <m-shah at ti.com>

Regards,
Moteen