[PATCH v7 00/41] KVM: arm64: Introduce vGIC-v5 with PPI support
Sascha Bischoff
Sascha.Bischoff at arm.com
Thu Mar 19 08:49:42 PDT 2026
This is v7 of the patch series to add the virtual GICv5 [1] device
(vgic_v5). Only PPIs are supported by this initial series, and the
vgic_v5 implementation is restricted to the CPU interface,
only. Further patch series are to follow in due course, and will add
support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS.
v1, v2, v3, v4, v5, v6 of this series can be found at [2], [3], [4],
[5], [6], [7], respectively.
Headline changes since v5:
* Moved the arch timer code on GICv5 hosts to use the existing irq
domain and phys_active mechanism, rather than adding bespoke code to
directly mask/unmask the physical interrupt. This has been tested
for GICv5-native and GICv3-on-GICv5 guests.
* Introduced a irq_set_type() handler for GICv5 PPIs to the GICv5 host
irqchip driver. This is required to be able to layer a domain
hierarchy onto the PPI domain. The irq_set_type handler checks that
the trigger mode matches what is reported by the hardware, but
doesn't actually affect any state as PPIs on GICv5 are not
configurable.
* Tracked if native GICv5 support was registered or not when probing,
and now return -ENODEV if neither native GICv5 or legacy GICv3 KVM
devices were registered. This could happen with pKVM on a system
that doesn't support FEAT_GCIE_LEGACY, for example. Thanks Joey!
* Cleaned up the code that sets and clears irq_ops.
* Moved vgic_v5_set_ppi_ops() to use the generic irq_ops setter.
* Reworked when irq_ops get set in the arch timer code to minimise the
call points. This now happens in kvm_timer_vcpu_init(). NOTE: This
does require the init order of the timer and vcpus to be
swapped. From what I can tell this is OK, but I am definitely not
sure.
* General clean-up some some of the commit messages to more accurately
document the commits.
* Added some Reviewed-by tags - thanks Jonathan!
These changes are based on v7.0-rc4. I have pushed these changes to a
branch that can be found at [8].
Thank you for the feedback.
Sascha
[1] https://developer.arm.com/documentation/aes0070/latest
[2] https://lore.kernel.org/all/20251212152215.675767-1-sascha.bischoff@arm.com/
[3] https://lore.kernel.org/all/20251219155222.1383109-1-sascha.bischoff@arm.com/
[4] https://lore.kernel.org/all/20260109170400.1585048-1-sascha.bischoff@arm.com/
[5] https://lore.kernel.org/all/20260128175919.3828384-1-sascha.bischoff@arm.com/
[6] https://lore.kernel.org/all/20260226155515.1164292-1-sascha.bischoff@arm.com/
[7] https://lore.kernel.org/all/20260317113949.2548118-1-sascha.bischoff@arm.com/
[8] https://gitlab.arm.com/linux-arm/linux-sb/-/tree/gicv5_ppi_support_v7
Sascha Bischoff (41):
KVM: arm64: vgic-v3: Drop userspace write sanitization for
ID_AA64PFR0.GIC on GICv5
KVM: arm64: vgic: Rework vgic_is_v3() and add vgic_host_has_gicvX()
KVM: arm64: Return early from kvm_finalize_sys_regs() if guest has run
KVM: arm64: Init vcpu prior to the timers and PMU
KVM: arm64: vgic: Split out mapping IRQs and setting irq_ops
arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support
arm64/sysreg: Add GICR CDNMIA encoding
KVM: arm64: gic-v5: Add ARM_VGIC_V5 device to KVM headers
KVM: arm64: gic: Introduce interrupt type helpers
KVM: arm64: gic-v5: Add Arm copyright header
KVM: arm64: gic-v5: Detect implemented PPIs on boot
KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE
KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs
KVM: arm64: gic-v5: Add emulation for ICC_IAFFIDR_EL1 accesses
KVM: arm64: gic-v5: Trap and emulate ICC_IDR0_EL1 accesses
KVM: arm64: gic-v5: Add vgic-v5 save/restore hyp interface
KVM: arm64: gic-v5: Implement GICv5 load/put and save/restore
KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask
KVM: arm64: gic: Introduce queue_irq_unlock to irq_ops
KVM: arm64: gic-v5: Implement PPI interrupt injection
KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5
KVM: arm64: gic-v5: Clear TWI if single task running
KVM: arm64: gic-v5: Check for pending PPIs
KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes
KVM: arm64: Introduce set_direct_injection irq_op
KVM: arm64: gic-v5: Implement direct injection of PPIs
KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE
KVM: arm64: gic-v5: Create and initialise vgic_v5
KVM: arm64: gic-v5: Initialise ID and priority bits when resetting
vcpu
irqchip/gic-v5: Introduce minimal irq_set_type() for PPIs
KVM: arm64: gic-v5: Enlighten arch timer for GICv5
KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5
KVM: arm64: gic: Hide GICv5 for protected guests
KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests
KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them
KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot
KVM: arm64: gic-v5: Probe for GICv5 device
Documentation: KVM: Introduce documentation for VGICv5
KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI
KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest
KVM: arm64: selftests: Add no-vgic-v5 selftest
Documentation/virt/kvm/api.rst | 6 +-
.../virt/kvm/devices/arm-vgic-v5.rst | 50 ++
Documentation/virt/kvm/devices/index.rst | 1 +
Documentation/virt/kvm/devices/vcpu.rst | 5 +-
arch/arm64/include/asm/el2_setup.h | 2 +
arch/arm64/include/asm/kvm_asm.h | 2 +
arch/arm64/include/asm/kvm_host.h | 34 ++
arch/arm64/include/asm/kvm_hyp.h | 10 +
arch/arm64/include/asm/sysreg.h | 7 +
arch/arm64/include/asm/vncr_mapping.h | 3 +
arch/arm64/include/uapi/asm/kvm.h | 1 +
arch/arm64/kvm/arch_timer.c | 112 +++-
arch/arm64/kvm/arm.c | 62 ++-
arch/arm64/kvm/config.c | 123 ++++-
arch/arm64/kvm/emulate-nested.c | 68 +++
arch/arm64/kvm/hyp/include/hyp/switch.h | 27 +
arch/arm64/kvm/hyp/nvhe/Makefile | 2 +-
arch/arm64/kvm/hyp/nvhe/hyp-main.c | 16 +
arch/arm64/kvm/hyp/nvhe/switch.c | 15 +
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 8 +
arch/arm64/kvm/hyp/vgic-v5-sr.c | 166 ++++++
arch/arm64/kvm/hyp/vhe/Makefile | 2 +-
arch/arm64/kvm/nested.c | 5 +
arch/arm64/kvm/pmu-emul.c | 20 +-
arch/arm64/kvm/sys_regs.c | 176 +++++-
arch/arm64/kvm/vgic/vgic-init.c | 214 +++++---
arch/arm64/kvm/vgic/vgic-kvm-device.c | 107 +++-
arch/arm64/kvm/vgic/vgic-mmio.c | 40 +-
arch/arm64/kvm/vgic/vgic-v3.c | 2 +-
arch/arm64/kvm/vgic/vgic-v5.c | 503 +++++++++++++++++-
arch/arm64/kvm/vgic/vgic.c | 173 ++++--
arch/arm64/kvm/vgic/vgic.h | 53 +-
arch/arm64/tools/sysreg | 480 +++++++++++++++++
drivers/irqchip/irq-gic-v5.c | 18 +
include/kvm/arm_arch_timer.h | 11 +-
include/kvm/arm_pmu.h | 5 +-
include/kvm/arm_vgic.h | 191 ++++++-
include/linux/irqchip/arm-gic-v5.h | 27 +
include/linux/kvm_host.h | 1 +
include/uapi/linux/kvm.h | 2 +
tools/arch/arm64/include/uapi/asm/kvm.h | 1 +
tools/include/uapi/linux/kvm.h | 2 +
tools/testing/selftests/kvm/Makefile.kvm | 3 +-
.../testing/selftests/kvm/arm64/no-vgic-v3.c | 177 ------
tools/testing/selftests/kvm/arm64/no-vgic.c | 297 +++++++++++
tools/testing/selftests/kvm/arm64/vgic_v5.c | 228 ++++++++
.../selftests/kvm/include/arm64/gic_v5.h | 150 ++++++
47 files changed, 3217 insertions(+), 391 deletions(-)
create mode 100644 Documentation/virt/kvm/devices/arm-vgic-v5.rst
create mode 100644 arch/arm64/kvm/hyp/vgic-v5-sr.c
delete mode 100644 tools/testing/selftests/kvm/arm64/no-vgic-v3.c
create mode 100644 tools/testing/selftests/kvm/arm64/no-vgic.c
create mode 100644 tools/testing/selftests/kvm/arm64/vgic_v5.c
create mode 100644 tools/testing/selftests/kvm/include/arm64/gic_v5.h
--
2.34.1
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