[PATCH v2 3/5] can: flexcan: add NXP S32N79 SoC support

[Ciprian Marian Costea]

On 3/19/2026 12:54 PM, Marc Kleine-Budde wrote:
> On 19.03.2026 10:40:30, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
>>
>> Add device data and compatible string for NXP S32N79 SoC.
>>
>> FlexCAN IP integration on S32N79 SoC uses two interrupts:
>> - one for mailboxes 0-127
>> - one for signaling bus errors and device state changes
>>
>> Co-developed-by: Andra-Teodora Ilie <andra.ilie at nxp.com>
>> Signed-off-by: Andra-Teodora Ilie <andra.ilie at nxp.com>
>> Co-developed-by: Larisa Grigore <larisa.grigore at nxp.com>
>> Signed-off-by: Larisa Grigore <larisa.grigore at nxp.com>
>> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
>> ---
>>   drivers/net/can/flexcan/flexcan-core.c | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
>> index 1d5879510adc..0f8ad666df09 100644
>> --- a/drivers/net/can/flexcan/flexcan-core.c
>> +++ b/drivers/net/can/flexcan/flexcan-core.c
>> @@ -397,6 +397,15 @@ static const struct flexcan_devtype_data nxp_s32g2_devtype_data = {
>>   		FLEXCAN_QUIRK_SECONDARY_MB_IRQ,
>>   };
>>
>> +static const struct flexcan_devtype_data nxp_s32n_devtype_data = {
>> +	.quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
>> +		FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
>> +		FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
>> +		FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_IRQ_BERR |
>> +		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX |
>> +		FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR,
>> +};
>> +
> 
> Nitpick: please order the quirks by value.
> 
> regards,
> Marc
> 

Sounds good. I can order them in V3.

Best Regards,
Ciprian