[PATCH v2] dmaengine: xilinx_dma: Fix reset related timeout with two-channel AXIDMA

[Vinod Koul]

On Wed, 11 Mar 2026 07:34:46 +0200, Tomi Valkeinen wrote:
> A single AXIDMA controller can have one or two channels. When it has two
> channels, the reset for both are tied together: resetting one channel
> resets the other as well. This creates a problem where resetting one
> channel will reset the registers for both channels, including clearing
> interrupt enable bits for the other channel, which can then lead  to
> timeouts as the driver is waiting for an interrupt which never comes.
> 
> [...]

Applied, thanks!

[1/1] dmaengine: xilinx_dma: Fix reset related timeout with two-channel AXIDMA
      commit: a17ce4bc6f4f9acf77ba416c36791a15602e53aa

Best regards,
-- 
~Vinod