[PATCH v2 1/2] clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src

[Quentin Schulz]

Hi Heiko,

On 3/4/26 1:14 PM, Heiko Stuebner wrote:
> From: Heiko Stuebner <heiko.stuebner at cherry.de>
> 
> dclk_vop2_src currently has the CLK_SET_RATE_PARENT flag set, which is
> very different from dclk_vop0_src or dclk_vop1_src, which don't have it.
> 
> With this flag in dclk_vop2_src, actually setting the clock then results
> in a lot of other peripherals breaking, because setting the rate results
> in the PLL source getting changed:
> 
> [   14.898718] clk_core_set_rate_nolock: setting rate for dclk_vop2 to 152840000
> [   15.155017] clk_change_rate: setting rate for pll_gpll to 1680000000
> [ clk adjusting every gpll user ]
> 
> This includes possibly the other vops, i2s, spdif and even the uarts.
> Among other possible things, this breaks the uart console on a board
> I use. Sometimes it recovers later on, but there will be a big block
> of garbled output for a while at least.
> 
> Shared PLLs should not be changed by individual users, so drop this flag
> from dclk_vop2_src.
> 
> Fixes: f1c506d152ff ("clk: rockchip: add clock controller for the RK3588")
> Cc: stable at vger.kernel.org
> Tested-by: Quentin Schulz <quentin.schulz at cherry.de> # RK3588 Tiger w/ DP

Reviewed-by: Quentin Schulz <quentin.schulz at cherry.de>

Thanks!
Quentin