[EXT] [PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

[Forrest Shi]

-----Original Message-----
From: Rob Herring (Arm) <robh at kernel.org> 
Sent: Saturday, March 7, 2026 4:31 AM
To: Forrest Shi <xuelin.shi at nxp.com>; Peng Fan (OSS) <peng.fan at oss.nxp.com>; Krzysztof Kozlowski <krzk+dt at kernel.org>; Conor Dooley <conor+dt at kernel.org>; Frank Li <frank.li at nxp.com>; Sascha Hauer <s.hauer at pengutronix.de>; Pengutronix Kernel Team <kernel at pengutronix.de>; Fabio Estevam <festevam at gmail.com>
Cc: Peter Robinson <pbrobinson at gmail.com>; devicetree at vger.kernel.org; imx at lists.linux.dev; linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org
Subject: [EXT] [PATCH v2] arm64: dts: freescale: imx93: Add Ethos-U65 NPU and SRAM nodes

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i.MX93 contains an Arm Ethos-U65 NPU. The NPU uses the internal SRAM for temporary buffers. The SRAM is larger than 96KB, but that is all that is available to non-secure world.

Signed-off-by: Rob Herring (Arm) <robh at kernel.org>
---
v2:
 - Increase the APB freq to 133MHz
---
 arch/arm64/boot/dts/freescale/imx93.dtsi | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi
index 7b27012dfcb5..95cc60158349 100644
--- a/arch/arm64/boot/dts/freescale/imx93.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93.dtsi
@@ -43,6 +43,29 @@ map0 {
                        };
                };
        };
+
+       sram: sram at 20480000 {
+               compatible = "mmio-sram";
+               reg = <0x0 0x20480000 0x0 0x18000>;
[Forrest Shi]  should it be 0x60000, 384KB? From NXP imx93 reference manual, there is one dedicated OCRAM for ethosu usage.
                       And this area is managed and accessed only by ethosu via command stream.
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x0 0x20480000 0x18000>;
[Forrest Shi]  same as above, 384KB?
+       };
+
+       soc at 0 {
+               npu at 4a900000 {
+                       compatible = "fsl,imx93-npu", "arm,ethos-u65";
+                       reg = <0x4a900000 0x1000>;
+                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&mlmix>;
+                       clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                       clock-names = "core", "apb";
+                       sram = <&sram>;
+                       assigned-clocks = <&clk IMX93_CLK_ML>, <&clk IMX93_CLK_ML_APB>;
+                       assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
+                       assigned-clock-rates = <800000000>, <133000000>;
+               };
+       };
 };

 &aips1 {
--
2.51.0