[PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder

[Krzysztof Kozlowski]

On 05/03/2026 12:35, Neil Armstrong wrote:
> On 3/5/26 12:08, Krzysztof Kozlowski wrote:
>> On 05/03/2026 12:01, Zhentao Guo wrote:
>>>
>>>        2. Why canvas is needed?
>>>
>>>   1. Since the ARM IOMMU HW is not integrated into the Amlogic SOCs,we
>>>      need canvas to prevent the DDR memory used by the decoder from being
>>>      rewrote by other hardware. Canvas provides the decoder with a
>>>      configurable DDR memory range, as well as hardware-based detection
>>>      and blocking for out-of-bounds access.
>>>    2. From the diagram above, we can see a lite CPU called AMRISC. AMRISC
>>>      is the controller of the decoder HW and the decoder driver needs to
>>>      access the decoder hardware through AMRISC. However, AMRISC is a
>>>      16-bit CPU and cannot directly handle 32-bit or 64-bit physical
>>>      addresses. Therefore, canvas is required to convert the addresses
>>>      into index to facilitate processing by the AMRISC core.
>>
>> This suggests "Canvas" is IOMMU, thus use proper IOMMU abstractions and
>> you cannot have own phandle for it.
> 
> 
> No it is not, canvas was used for a long time for the display and video processing side.
> 
> It's absolutely not like an IOMMU, the diagram is quite clear.

The diagram and all descriptions points to memory mapping...

"Canvas index is basically a reference to a memory region and its
configurations."
"Memory access through canvas has HW out-of-boundary check. "
"Canvas provides the decoder with a configurable DDR memory range"
"canvas is required to convert the addresses into index to..."

so it is not a random phandle either.


Best regards,
Krzysztof