[PATCH v4] dt-bindings: dma: xlnx,axi-dma: Convert to DT schema

[Frank Li]

On Wed, Mar 04, 2026 at 11:56:46PM +0530, Abin Joseph wrote:
> Convert the bindings document for Xilinx DMA.
> No changes to existing binding description.
>
> Signed-off-by: Abin Joseph <abin.joseph at amd.com>
> ---
>
...
> +
> +maintainers:
> +  - Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
> +  - Abin Joseph <abin.joseph at amd.com>
> +
> +description: |

I remember rob suggest use > instead of | to keep paragraph.

> +  Xilinx AXI VDMA engine, it does transfers between memory and video devices.
> +  It can be configured to have one channel or two channels. If configured
> +  as two channels, one is to transmit to the video device and another is
> +  to receive from the video device.
...
> +
> +required:
> +  - "#dma-cells"
> +  - reg
> +  - xlnx,addrwidth
> +  - dma-ranges
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false

Use unevaluatedProperties: false because ref to dma-controller.yaml
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    dma-controller at 40030000 {
> +        compatible = "xlnx,axi-vdma-1.00.a";

reg should second one.

> +        #dma-cells = <1>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        reg = <0x40030000 0x10000>;
> +        dma-ranges = <0x0 0x0 0x40000000>;
> +        xlnx,num-fstores = <8>;
> +        xlnx,flush-fsync;
> +        xlnx,addrwidth = <32>;

vendor property should be last, after clock-names.

Frank
> +        clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
> +        clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk",
> +                      "m_axi_s2mm_aclk", "m_axis_mm2s_aclk",
> +                      "s_axis_s2mm_aclk";
> +
...
> --
> 2.43.0
>