[PATCH 2/3] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board

[Nazle Asmade, Muhammad Nazim Amirul]

On 30/6/2026 9:58 pm, Andrew Lunn wrote:
>> + * gmac1 is the TSN port. The MAC operates in GMII mode internally
>> + * while the PHY-side interface is RGMII, so mac-mode and phy-mode differ.
>> + */
>> +&gmac1 {
>> +	status = "okay";
>> +	phy-mode = "rgmii"; /* TX/RX clock delays provided by Agilex5 I/O hardware */
> Could you provide more details about this. I want to understand the
> big picture.
> 
> Normally we talk about the PCB providing the delays. This sounds like
> it is the FPGA? So i need convincing this is correct.
Hi Andrew,

Thanks for your quick review and yes, it is the FPGA — specifically a 
soft IP block in the FPGA fabric that implements the RGMII clock delays 
and is configured before Linux boots via the FPGA bitstream. The driver 
must not add additional delays on top.

BR,
Nazim