[PATCH v4] arm64: dts: imx94: Add Root Port node and PERST property

[Frank Li]

On Tue, Jun 16, 2026 at 03:23:34PM +0800, hongxing.zhu at oss.nxp.com wrote:
> From: Richard Zhu <hongxing.zhu at nxp.com>
>
> Since describing the PCIe PERST# property under Host Bridge node is now
> deprecated, it is recommended to add it to the Root Port node, so
> creating the Root Port node and add the reset-gpios property in Root
> Port.
> Move the regulator to Root Port nodes as well, because that the PCI
> pwrctrl framework had been integrated into pci-imx6 driver.
>
> Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> Reviewed-by: Sherry Sun <sherry.sun at nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx94.dtsi     | 11 +++++++++++
>  arch/arm64/boot/dts/freescale/imx943-evk.dts | 14 ++++++++++----
>  arch/arm64/boot/dts/freescale/imx943.dtsi    | 11 +++++++++++

use two patch, one patch only change chip's dtsi, the other one update
boards's dts

Frank

>  3 files changed, 32 insertions(+), 4 deletions(-)
> ---
> Changes in v4:
> Add the description of regualtor changes into commit message too.
>
> Changes in v3:
> - Move the regulator to Root Port node as well, since [2] had been
>   settled.
> - Collect Reviewed-by tag issued by Sherry.
>
> Changes in v2:
> - Delete reset-gpio properties in PCIe bridge node.
> - Correct the "reset-gpio" property to "reset-gpios".
>
> Since the patch-set [1] issued by Sherry had been landed. Add according
> changes on i.MX943 board too.
> [1] https://lkml.org/lkml/2026/6/1/1461
> [2] https://lore.kernel.org/imx/20260520084904.2424253-1-sherry.sun@oss.nxp.com/
>
> diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
> index 1f9035e6cf159..dfbb73603cb24 100644
> --- a/arch/arm64/boot/dts/freescale/imx94.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
> @@ -1411,6 +1411,17 @@ pcie0: pcie at 4c300000 {
>  			power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
>  			fsl,max-link-speed = <3>;
>  			status = "disabled";
> +
> +			pcie0_port0: pcie at 0 {
> +				compatible = "pciclass,0604";
> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +			};
>  		};
>
>  		pcie0_ep: pcie-ep at 4c300000 {
> diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> index 7cfd424689507..674410e541cba 100644
> --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> @@ -1034,12 +1034,15 @@ &pcie0 {
>  		 <&pcie_ref_clk>;
>  	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
>  		      "ref", "extref";
> -	reset-gpio = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
> -	vpcie3v3aux-supply = <&reg_m2_wlan>;
>  	supports-clkreq;
>  	status = "okay";
>  };
>
> +&pcie0_port0 {
> +	reset-gpios = <&pcal6416_i2c3_u46 3 GPIO_ACTIVE_LOW>;
> +	vpcie3v3aux-supply = <&reg_m2_wlan>;
> +};
> +
>  &pcie0_ep {
>  	pinctrl-0 = <&pinctrl_pcie0>;
>  	pinctrl-names = "default";
> @@ -1058,12 +1061,15 @@ &pcie1 {
>  		 <&pcie_ref_clk>;
>  	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux",
>  		      "ref", "extref";
> -	reset-gpio = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
> -	vpcie3v3aux-supply = <&reg_slot_pwr>;
>  	supports-clkreq;
>  	status = "okay";
>  };
>
> +&pcie1_port0 {
> +	reset-gpios = <&pcal6416_i2c3_u46 1 GPIO_ACTIVE_LOW>;
> +	vpcie3v3aux-supply = <&reg_slot_pwr>;
> +};
> +
>  &pcie1_ep {
>  	pinctrl-0 = <&pinctrl_pcie1>;
>  	pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index cf5b3dbb47ff7..01152fd0efa5e 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -255,6 +255,17 @@ pcie1: pcie at 4c380000 {
>  			power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>;
>  			fsl,max-link-speed = <3>;
>  			status = "disabled";
> +
> +			pcie1_port0: pcie at 0 {
> +				compatible = "pciclass,0604";
> +				device_type = "pci";
> +				reg = <0x0 0x0 0x0 0x0 0x0>;
> +				bus-range = <0x01 0xff>;
> +
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				ranges;
> +			};
>  		};
>
>  		pcie1_ep: pcie-ep at 4c380000 {
> --
> 2.34.1
>