[PATCH v4 4/4] arm64: escalate smp_send_stop() to an SDEI NMI as a last resort

[Catalin Marinas]

On Wed, Jun 17, 2026 at 08:20:05PM +0100, Kiryl Shutsemau wrote:
> +void sdei_nmi_stop_cpus(const cpumask_t *mask)
> +{
> +	unsigned int cpu;
> +
> +	WRITE_ONCE(sdei_nmi_stopping, true);
> +
> +	/*
> +	 * Publish the flag before signalling. The SMC is a context-sync
> +	 * event, not a barrier, so WRITE_ONCE() alone could let the store be
> +	 * observed after the event it triggers. The barrier is cumulative: a
> +	 * target that sees the event is guaranteed to see the flag.
> +	 */
> +	smp_wmb();
> +
> +	for_each_cpu(cpu, mask)
> +		sdei_nmi_fire(cpu);
> +}

The smp_wmb() is not sufficient here. In the GIC IPI code we use a
dsb(ishst). It should be similar here. I think TF-A does this already
but it's unclear from the SDEI spec that it is mandated.

-- 
Catalin