[PATCH v5 8/8] arm64: dts: imx8qxp-mek: add parallel ov5640 camera support

[guoniu.zhou at oss.nxp.com]

> Add parallel ov5640 nodes in imx8qxp-mek and create overlay file to enable
> it because it can work at two mode: MIPI CSI and parallel mode.
> 
> Signed-off-by: Frank Li <Frank.Li at nxp.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 711e36cc2c99..f54fd4cdd926 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -434,6 +434,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb
>  imx8qxp-mek-ov5640-csi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dtbo
>  dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb
>  
> +imx8qxp-mek-ov5640-cpi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-cpi.dtbo
> +dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-cpi.dtb
> +
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso
> new file mode 100644
> index 000000000000..9fbdd798f17d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2025 NXP
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +#include <dt-bindings/clock/imx8-lpcg.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/media/video-interfaces.h>
> +#include <dt-bindings/pinctrl/pads-imx8qxp.h>
> +
> +&cm40_i2c {
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +
> +	ov5640_pi: camera at 3c {
> +		compatible = "ovti,ov5640";
> +		reg = <0x3c>;
> +		clocks = <&pi0_misc_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "xclk";
> +		assigned-clocks = <&pi0_misc_lpcg IMX_LPCG_CLK_0>;
> +		assigned-clock-rates = <24000000>;
> +		AVDD-supply = <&reg_2v8>;
> +		DOVDD-supply = <&reg_1v8>;
> +		DVDD-supply = <&reg_1v5>;
> +		pinctrl-0 = <&pinctrl_parallel_cpi>;
> +		pinctrl-names = "default";
> +		powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>;
> +		reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
> +
> +		port {
> +			ov5640_pi_ep: endpoint {
> +				bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
> +				bus-width = <8>;
> +				hsync-active = <1>;
> +				pclk-sample = <1>;
> +				remote-endpoint = <&parallel_cpi_in>;
> +				vsync-active = <0>;
> +			};
> +		};
> +	};
> +};
> +
> +&iomuxc {
> +	pinctrl_parallel_cpi: parallelcpigrp {
> +		fsl,pins = <
> +			IMX8QXP_CSI_D00_CI_PI_D02		0xc0000041
> +			IMX8QXP_CSI_D01_CI_PI_D03		0xc0000041
> +			IMX8QXP_CSI_D02_CI_PI_D04		0xc0000041
> +			IMX8QXP_CSI_D03_CI_PI_D05		0xc0000041
> +			IMX8QXP_CSI_D04_CI_PI_D06		0xc0000041
> +			IMX8QXP_CSI_D05_CI_PI_D07		0xc0000041
> +			IMX8QXP_CSI_D06_CI_PI_D08		0xc0000041
> +			IMX8QXP_CSI_D07_CI_PI_D09		0xc0000041
> +
> +			IMX8QXP_CSI_MCLK_CI_PI_MCLK		0xc0000041
> +			IMX8QXP_CSI_PCLK_CI_PI_PCLK		0xc0000041
> +			IMX8QXP_CSI_HSYNC_CI_PI_HSYNC		0xc0000041
> +			IMX8QXP_CSI_VSYNC_CI_PI_VSYNC		0xc0000041
> +			IMX8QXP_CSI_EN_LSIO_GPIO3_IO02		0xc0000041
> +			IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03	0xc0000041
> +		>;
> +	};
> +};
> +
> +&isi {
> +	status = "okay";
> +};
> +
> +&parallel_cpi {
> +	status = "okay";
> +
> +	ports {
> +		port at 0 {
> +			parallel_cpi_in: endpoint {
> +				hsync-active = <1>;
> +				remote-endpoint = <&ov5640_pi_ep>;
> +			};
> +		};
> +	};
> +};

Reviewed-by: Guoniu Zhou <guoniu.zhou at nxp.com>

-- 
Guoniu Zhou <guoniu.zhou at oss.nxp.com>