[PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller

[Joakim Zhang]

Hello,


> -----Original Message-----
> From: Philipp Zabel <p.zabel at pengutronix.de>
> Sent: Thursday, June 18, 2026 4:30 PM
> To: Joakim Zhang <joakim.zhang at cixtech.com>; Conor Dooley
> <conor at kernel.org>
> Cc: mturquette at baylibre.com; sboyd at kernel.org; bmasney at redhat.com;
> robh at kernel.org; krzk+dt at kernel.org; conor+dt at kernel.org; Gary Yang
> <Gary.Yang at cixtech.com>; cix-kernel-upstream <cix-kernel-
> upstream at cixtech.com>; linux-clk at vger.kernel.org;
> devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v4 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss
> clock controller
> 
> EXTERNAL EMAIL
> 
> CAUTION: Suspicious Email from unusual domain.
> 
> On Do, 2026-06-18 at 01:43 +0000, Joakim  Zhang wrote:
> > Hello,
> >
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor at kernel.org>
> > > Sent: Wednesday, June 17, 2026 11:56 PM
> > > To: Joakim Zhang <joakim.zhang at cixtech.com>
> > > Cc: mturquette at baylibre.com; sboyd at kernel.org; bmasney at redhat.com;
> > > robh at kernel.org; krzk+dt at kernel.org; conor+dt at kernel.org;
> > > p.zabel at pengutronix.de; Gary Yang <gary.yang at cixtech.com>;
> > > cix-kernel- upstream <cix-kernel-upstream at cixtech.com>;
> > > linux-clk at vger.kernel.org; devicetree at vger.kernel.org;
> > > linux-kernel at vger.kernel.org; linux-arm- kernel at lists.infradead.org
> > > Subject: Re: [PATCH v4 3/5] dt-bindings: clock:
> > > cix,sky1-audss-clock: add audss clock controller
> > >
> > > On Wed, Jun 17, 2026 at 02:04:35PM +0800, joakim.zhang at cixtech.com
> wrote:
> > > > From: Joakim Zhang <joakim.zhang at cixtech.com>
> > > >
> > > > The AUDSS CRU contains an internal clock tree of muxes, dividers
> > > > and gates for DSP, I2S, HDA, DMAC and related blocks. The clock
> > > > provider is a child node of the cix,sky1-audss-system-control
> > > > syscon and accesses registers through the parent MMIO region.
> > >
> > > Why can this not just be part of the parent syscon node?
> >
> > The clock and reset blocks are handled by different subsystems and
> maintainers (clk vs reset). Putting the clock provider on the parent syscon node
> would mean a single driver has to register both the reset controller and the
> clock provider on one device, which doesn't fit well.
> 
> There are many examples of clock and reset drivers sharing the same node, by
> using platform_driver for one (usually clk) and auxiliary_driver for the other
> (usually reset).

OK, I will have a look.  If you are also prefer to this, I will refactor the patch.

Thanks,
Joakim