[PATCH v9 9/9] perf test: Add Arm CoreSight callchain test

[James Clark]

On 17/06/2026 4:08 pm, Leo Yan wrote:
> On Wed, Jun 17, 2026 at 01:33:22PM +0100, Coresight ML wrote:
>> On Wed, Jun 17, 2026 at 11:03:07AM +0100, James Clark wrote:
>>
>> [...]
>>
>>>> +	# It is safe to use 'i3i' with a three-instruction interval, since the
>>>> +	# workload is compiled with -O0.
>>>> +	perf script --itrace=g16i3il64 -i "$data" > "$script"
>>>
>>> Is there a reason we don't generate callstacks on branch samples and use
>>> --itrace=g16bl64? That removes the magic number 3 and reduces the output
>>> file size and test runtime a bit.
>>
>> I checked Intel-PT which does not generate callchain and branch stack for
>> branch samples. I just keep cs-etm aligned.
>>
>> I can add callstack / branch stack for branch samples.
> 
> Tried a bit for this.
> 
> The branch stack is skipped due the check:
> 
>    if (is_bts_event(attr)) {
>            perf_sample__fprintf_bts(sample, evsel, thread, al, addr_al, machine, fp);
>            return;
>    }
> 
> For the callstack attached to branch samples, the output seems not
> directive:
> 
>    callchain_test    4372 [003] 75596.459422:          1 branches:
>              aaaaabdb0794 print+0x8 (/home/kernel/leoy/test_cs_callchain/callchain_test)
>              aaaaabdb0798 print+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test)
>              aaaaabdb07b0 foo+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test)
>              aaaaabdb07c8 main+0xc (/home/kernel/leoy/test_cs_callchain/callchain_test)
>              ffff9a10225c __libc_start_call_main+0x7c (/usr/lib/aarch64-linux-gnu/libc.so.6)
>              ffff9a10233c call_init+0x9c (inlined)
>              ffff9a10233c __libc_start_main_impl+0x9c (inlined)
>              aaaaabdb0670 _start+0x30 (/home/kernel/leoy/test_cs_callchain/callchain_test)
>              ffff9a2206a0 __libc_early_init+0x100 (/usr/lib/aarch64-linux-gnu/libc.so.6)
>   =>     aaaaabdb0768 do_svc+0x0 (/home/kernel/leoy/test_cs_callchain/callchain_test)
> 
> It is hard to digest the log as it separates branch from address
> (aaaaabdb0794 print+0x8) and to address (aaaaabdb0768 do_svc+0x0),
> and put the callchain in the middle of from and to ranges.
> 
> Given this is not enabled by other hardware trace (e.g., Intel-PT),
> and we need to change the common code to make it better, I'd first
> enable callchain/branch stack for instruction samples. Let's see if
> further requirement after get this done.
> 
> Thanks,
> Leo

Yep that sounds ok to me