[PATCH v4 0/5] Add Cix Sky1 AUDSS clock and reset support

[Joakim Zhang]

Sorry for the disturb, I will resend the patch set to fix a typo.

Joakim

> -----Original Message-----
> From: joakim.zhang at cixtech.com <joakim.zhang at cixtech.com>
> Sent: Wednesday, June 17, 2026 2:05 PM
> To: mturquette at baylibre.com; sboyd at kernel.org; bmasney at redhat.com;
> robh at kernel.org; krzk+dt at kernel.org; conor+dt at kernel.org;
> p.zabel at pengutronix.de; Gary Yang <gary.yang at cixtech.com>
> Cc: cix-kernel-upstream <cix-kernel-upstream at cixtech.com>; linux-
> clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; Joakim Zhang
> <joakim.zhang at cixtech.com>
> Subject: [PATCH v4 0/5] Add Cix Sky1 AUDSS clock and reset support
> 
> From: Joakim Zhang <joakim.zhang at cixtech.com>
> 
> This patch set adds the clock and reset support for AUDSS. The AUDSS groups
> audio-related peripherals (HDA, I2S, DSP, DMA, mailboxes, watchdog, timer,
> etc.) behind a single Clock and Reset Unit (CRU) register block.
> 
> Clock and reset changes normally belong to separate subsystems and would
> ideally be submitted as independent series. They are combined here because
> the AUDSS DT bindings cross-reference each other: the system-control binding
> describes the clock child node, the clock binding documents reset lines exposed
> on the parent syscon, and the DTS example wires both together. Keeping clock
> and reset in one series gives reviewers the full picture when evaluating the
> binding layout, dependencies, and integration.
> 
> Patches apply in the following order:
> 
>   1. Reset support
>      - dt-bindings: soc: cix,sky1-system-control: add audss system control
>      - reset: cix: add audss support to sky1 reset driver
> 
>   2. Clock support
>      - dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
>      - clk: cix: add sky1 audss clock controller
> 
>   3. Device tree
>      - arm64: dts: cix: sky1: add audss system control
> 
> The reset and clock parts have each been build-tested and checked with
> dt_binding_check independently. If reviewers prefer separate series for the
> reset and clock maintainers, I can split and resubmit after this round of review
> once the overall design is agreed on.
> 
> ---
> ChangeLogs:
> v3->v4:
>   * move both power domain and resets into parset node (audss_cru)
>   * remove "simple-mfd", and change to populate the child node
>   * cix,sky1-audss.h -> cix,sky1-audss-clock.h
> 
> v2->v3:
>   * clk part:
>     * devm_reset_control_get()->devm_reset_control_get_exclusive()
>     * assert noc reset from suspend
>     * clock parents changes from 6 to 4, and rename the clock names,
>       explain more about this: confirm with our designer, In fact,
>       there are 6 clock sources going into the audio subsystem. audio_clk1
>       and audio_clk3 are redundant in design and are not actually needed
>       in practice, so they are not shown here.
>     * refine clocks and clock-names property
>     * add detailed description of clocks
>     * drop parent node from clk binding
>     * drop define AUDSS_MAX_CLKS
>   * reset part:
>     * rename reset signal macro, remove _N
>     * drop SKY1_AUDSS_SW_RESET_NUM
>     * switching to compatible-style of defining subnodes in parent schema
> 
> v1->v2:
>   * remove audss_rst device node since it doesn't has resource, and
>     move to reset-sky1.c driver.
>   * remove hda related which would be sent after this patch set accepted
>   * soc componnet is okay by default from dtsi
>   * fix for audss clk driver:
>     * remove "comment "Clock options for Cixtech audss:""
>     * add select MFD_SYSCON
>     * move lock and clk_data into struct sky1_audss_clks_priv
>     * const char *name -> const char * const * name
>     * remove CLK_GET_RATE_NOCACHE
>     * divicer -> divider
>     * Reverse Christmas tree order
>     * return reg ? 1 : 0; -> return !!reg;
>     * return ERR_CAST(hw); -> return hw;
>     * of_device_get_match_data(dev) -> device_get_match_data()
>     * add lock from runtime_suspend/resume
>   * loop to more mailing lists
> 
> Joakim Zhang (5):
>   dt-bindings: soc: cix,sky1-system-control: add audss system control
>   reset: cix: add audss support to sky1 reset driver
>   dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
>   clk: cix: add sky1 audss clock controller
>   arm64: dts: cix: sky1: add audss system control
> 
>  .../bindings/clock/cix,sky1-audss-clock.yaml  |   72 +
>  .../soc/cix/cix,sky1-system-control.yaml      |   48 +
>  arch/arm64/boot/dts/cix/sky1.dtsi             |   24 +
>  drivers/clk/Kconfig                           |    1 +
>  drivers/clk/Makefile                          |    1 +
>  drivers/clk/cix/Kconfig                       |   16 +
>  drivers/clk/cix/Makefile                      |    3 +
>  drivers/clk/cix/clk-sky1-audss.c              | 1167 +++++++++++++++++
>  drivers/reset/reset-sky1.c                    |   86 +-
>  .../dt-bindings/clock/cix,sky1-audss-clock.h  |   60 +
>  .../reset/cix,sky1-audss-system-control.h     |   25 +
>  11 files changed, 1500 insertions(+), 3 deletions(-)  create mode 100644
> Documentation/devicetree/bindings/clock/cix,sky1-audss-clock.yaml
>  create mode 100644 drivers/clk/cix/Kconfig  create mode 100644
> drivers/clk/cix/Makefile  create mode 100644 drivers/clk/cix/clk-sky1-audss.c
> create mode 100644 include/dt-bindings/clock/cix,sky1-audss-clock.h
>  create mode 100644 include/dt-bindings/reset/cix,sky1-audss-system-control.h
> 
> --
> 2.50.1