[PATCH] arm64: tlb: Flush walk cache when unsharing PMD tables

[David Hildenbrand (Arm)]

On 5/21/26 17:05, Catalin Marinas wrote:
> + David H.
> 
> On Thu, May 21, 2026 at 03:30:11PM +0800, Zeng Heng wrote:
>> From: Zeng Heng <zengheng4 at huawei.com>
>>
>> When huge_pmd_unshare() is called to unshare a PMD table, the
>> tlb_unshare_pmd_ptdesc() function sets tlb->unshared_tables=true
>> but the aarch64 tlb_flush() only checked tlb->freed_tables to
>> determine whether to use TLBF_NONE (vae1is, invalidates walk
>> cache) or TLBF_NOWALKCACHE (vale1is, leaf-only).
>>
>> This caused the stale PMD page table entry to remain in the walk cache
>> after unshare, potentially leading to incorrect page table walks.
>>
>> Fix by including unshared_tables in the check, so that when
>> unsharing tables, TLBF_NONE is used and the walk cache is properly
>> invalidated.
>>
>> Here is the detailed distinction between vae1is and vale1is:
>>
>> | Instruction Combination  | Actual Invalidation Scope                         |
>> | ------------------------ | --------------------------------------------------|
>> | `VAE1IS`  + TTL=`0`      | All entries at all levels (full invalidation)     |
>> | `VAE1IS`  + TTL=`2` (L2) | Non-leaf at Level 0/1 + leaf at Level 2           |
>> | `VALE1IS` + TTL=`0`      | Leaf entries at all levels (non-leaf not cleared) |
>> | `VALE1IS` + TTL=`2` (L2) | Leaf entry at Level 2 only                        |
>>
>> Signed-off-by: Zeng Heng <zengheng4 at huawei.com>
> 
> The fix looks fine but does it need:

I'm late ... just stumbled over this in my inbox while digging though a pile.

> 
> Fixes: 8ce720d5bd91 ("mm/hugetlb: fix excessive IPI broadcasts when unsharing PMD tables using mmu_gather")
> Cc: <stable at vger.kernel.org>

Very likely, yes.

> 
>> ---
>>  arch/arm64/include/asm/tlb.h | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
>> index 10869d7731b8..751bd57bc3ba 100644
>> --- a/arch/arm64/include/asm/tlb.h
>> +++ b/arch/arm64/include/asm/tlb.h
>> @@ -53,7 +53,8 @@ static inline int tlb_get_level(struct mmu_gather *tlb)
>>  static inline void tlb_flush(struct mmu_gather *tlb)
>>  {
>>  	struct vm_area_struct vma = TLB_FLUSH_VMA(tlb->mm, 0);
>> -	tlbf_t flags = tlb->freed_tables ? TLBF_NONE : TLBF_NOWALKCACHE;
>> +	tlbf_t flags = (tlb->freed_tables || tlb->unshared_tables) ?
>> +			TLBF_NONE : TLBF_NOWALKCACHE;
>>  	unsigned long stride = tlb_get_unmap_size(tlb);
>>  	int tlb_level = tlb_get_level(tlb);
>>  

Right, the old code would have effectively called flush_tlb_range() ->
flush_tlb_mm_range() with freed_tables=true.

I recall that being a tricky bit. The commit documents that as:

    (1) tlb_remove_table_sync_one() is a NOP on architectures without
        CONFIG_MMU_GATHER_RCU_TABLE_FREE.

        Here, the assumption is that the previous TLB flush would send an
        IPI to all relevant CPUs. Careful: some architectures like x86 only
        send IPIs to all relevant CPUs when tlb->freed_tables is set.

        The relevant architectures should be selecting
        MMU_GATHER_RCU_TABLE_FREE, but x86 might not do that in stable
        kernels and it might have been problematic before this patch.

        Also, the arch flushing behavior (independent of IPIs) is different
        when tlb->freed_tables is set. Do we have to enlighten them to also
        take care of tlb->unshared_tables? So far we didn't care, so
        hopefully we are fine. Of course, we could be setting
        tlb->freed_tables as well, but that might then unnecessarily flush
        too much, because the semantics of tlb->freed_tables are a bit
        fuzzy.


Turns out I was thinking too much in terms of optimizing IPIs.

Besides arm64 and x86, powerpc and riscv also rely on "tlb->freed_tables"
in tlb_flush(). But only arm64, x86 and riscv support ARCH_WANT_HUGE_PMD_SHARE.

Which makes me wonder whether we also need:


diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h
index 50b63b5c15bd..17c551322b5d 100644
--- a/arch/riscv/include/asm/tlb.h
+++ b/arch/riscv/include/asm/tlb.h
@@ -16,7 +16,8 @@ static void tlb_flush(struct mmu_gather *tlb);
 static inline void tlb_flush(struct mmu_gather *tlb)
 {
 #ifdef CONFIG_MMU
-       if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables)
+       if (tlb->fullmm || tlb->need_flush_all || tlb->freed_tables ||
+           tlb->unshared_tables)
                flush_tlb_mm(tlb->mm);
        else
                flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end,

CCing riscv maintainers.

-- 
Cheers,

David