[PATCH v3 2/2] clk: amlogic: Add A9 peripherals clock controller driver
Jian Hu
jian.hu at amlogic.com
Mon Jun 15 04:25:20 PDT 2026
On 6/10/2026 8:49 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On mer. 10 juin 2026 at 16:14, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com at kernel.org> wrote:
>
>> From: Jian Hu <jian.hu at amlogic.com>
>>
>> Add the peripherals clock controller driver for the Amlogic A9 SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu at amlogic.com>
>> ---
>> drivers/clk/meson/Kconfig | 15 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/a9-peripherals.c | 1925 ++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1941 insertions(+)
>>
[ ... ]
>> +
>> +/* Channel 6 is unconnected. */
>> +static u32 a9_glb_parents_val_table[] = { 0, 1, 2, 3, 4, 5, 7 };
>> +static struct clk_regmap a9_dspa;
> What is this ?
The peripheral clock definitions are ordered by register offset.
dspa is one of the parents of the glb clock, while the dsp clock
registers are located after the GLB clock registers.
Since glb references a9_dspa before its full definition appears, the
declaration
static struct clk_regmap a9_dspa;
is added as a forward declaration to satisfy the compiler.
Would it make sense to relax the register-offset ordering in this case?
By defining the DSP clock before the GLB clock, we could remove the
forward declaration of a9_dspa.
>> +
>> +static const struct clk_parent_data a9_glb_parents[] = {
>> + { .fw_name = "xtal", },
>> + { .hw = &a9_dspa.hw },
>> + { .fw_name = "fdiv3", },
>> + { .fw_name = "fdiv4", },
>> + { .fw_name = "fdiv5", },
>> + { .hw = &a9_isp.hw },
>> + { .fw_name = "rtc", }
>> +};
>> +
>> +static A9_COMP_SEL(glb, GLB_CLK_CTRL, 9, 0x7, a9_glb_parents,
>> + a9_glb_parents_val_table);
>> +static A9_COMP_DIV(glb, GLB_CLK_CTRL, 0, 7);
>> +static A9_COMP_GATE(glb, GLB_CLK_CTRL, 8, 0);
>> +
>> +static struct clk_regmap a9_usb_48m_dualdiv_in = {
>> + .data = &(struct clk_regmap_gate_data) {
>> + .offset = USB_CLK_CTRL,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("usb_48m_dualdiv_in", &a9_usb_48m_pre.hw,
>> + &clk_regmap_gate_ops, 0),
> Same comment as on the AO controller
Ok, I will drop CLK_HW_INIT*, and apply the same change to the other
clock definitions.
[ ... ]
>> +
>> +/* Channel 3 is unconnected. */
> You meant 3rd I guess but this is misleading and confusing with the
> table bellow. Channel 2 would be more appropriate I think, since those
> are 0-based.
You are right, The 3rd channel is unconnected. I will fix it in the
next version.
>> +static u32 a9_can_pe_parents_val_table[] = { 0, 1, 3 };
>> +static const struct clk_parent_data a9_can_pe_parents[] = {
>> + { .fw_name = "sys", },
>> + { .fw_name = "xtal", },
>> + { .fw_name = "fdiv5", }
>> +};
>> +
[ ... ]
>> +
>> +/*
>> + * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module;
>> + * channel 12(msr_clk) is manged by clock measures module.
>> + * channel 16(audio_dac1_clk) is manged by audio module.
> Some why can't you expose those then ? gen clk is used for debugging
> AFAIK. The clock above are worth debugging I think
>
> Please be consistent with the CaSing.
For channel 3 (ddr_dpll_pt_clk), it is sourced from the DDR PLL clock
controller rather than
this clock controller. I will expose it in the DT.
For channel 12 (msr_clk), it depends on the clock measurement
configuration.
The measurement source must first be selected through freq_ctrl[20:26], and
only then does msr_clk become meaningful. In practice.
It is not a real clock but an output of the measurement logic, so it can
not be exposed as a clock.
https://elixir.bootlin.com/linux/v7.1-rc7/source/drivers/soc/amlogic/meson-clk-measure.c#L809
For channel 16 (audio_dac1_clk), I confirmed with the clock hardware
designer that
it is actually unconnected. It looks like there is an error in the
documentation.
I'll also fix the casing to keep it consistent throughout the comments.
>> + * Channel 10, 11, 13, 14 are not connected.
>> + */
>> +static u32 a9_gen_parents_val_table[] = { 0, 1, 2, 4, 5, 6, 7, 8, 9, 15, 17, 18,
>> + 19, 20, 21, 22, 23, 24, 25, 26};
>> +static struct clk_regmap a9_vid_pll;
>> +
>> +static const struct clk_parent_data a9_gen_parents[] = {
>> + { .fw_name = "xtal" },
>> + { .fw_name = "rtc" },
>> + { .fw_name = "sysplldiv16" },
>> + { .hw = &a9_vid_pll.hw },
>> + { .fw_name = "gp0" },
>> + { .fw_name = "hifi1" },
>> + { .fw_name = "hifi0" },
>> + { .fw_name = "gp1" },
>> + { .fw_name = "gp2" },
>> + { .fw_name = "dsudiv16" },
>> + { .fw_name = "cpudiv16" },
>> + { .fw_name = "a78div16" },
>> + { .fw_name = "fdiv2" },
>> + { .fw_name = "fdiv2p5" },
>> + { .fw_name = "fdiv3" },
>> + { .fw_name = "fdiv4" },
>> + { .fw_name = "fdiv5" },
>> + { .fw_name = "fdiv7" },
>> + { .fw_name = "mclk0" },
>> + { .fw_name = "mclk1" }
>> +};
>> +
>> +static A9_COMP_SEL(gen, GEN_CLK_CTRL, 12, 0x1f, a9_gen_parents,
>> + a9_gen_parents_val_table);
>> +static A9_COMP_DIV(gen, GEN_CLK_CTRL, 0, 11);
>> +static A9_COMP_GATE(gen, GEN_CLK_CTRL, 11, 0);
>> +
[ ... ]
>> +
>> +static struct clk_regmap a9_enc, a9_enc1;
> What is this again ?? and please come up with better names.
Same as the previous dspa clock declaration.
enc stands for encoder. I'll rename a9_enc to a9_encoder0 and a9_enc1 to
a9_encoder1 in the next version.
>> +
>> +static const struct clk_parent_data a9_vid_lock_parents[] = {
>> + { .fw_name = "xtal", },
>> + { .hw = &a9_enc.hw },
>> + { .hw = &a9_enc1.hw }
>> +};
>> +
>> +static A9_COMP_SEL(vid_lock, VID_LOCK_CLK_CTRL, 9, 0x7, a9_vid_lock_parents,
>> + NULL);
>> +static A9_COMP_DIV(vid_lock, VID_LOCK_CLK_CTRL, 0, 7);
>> +static A9_COMP_GATE(vid_lock, VID_LOCK_CLK_CTRL, 8, 0);
>> +
>> +static const struct clk_parent_data a9_vdin_meas_parents[] = {
>> + { .fw_name = "xtal", },
>> + { .fw_name = "fdiv4", },
>> + { .fw_name = "fdiv3", },
>> + { .fw_name = "fdiv5", }
>> +};
>> +
>> +static A9_COMP_SEL(vdin_meas, VDIN_MEAS_CLK_CTRL, 9, 0x7, a9_vdin_meas_parents,
>> + NULL);
>> +static A9_COMP_DIV(vdin_meas, VDIN_MEAS_CLK_CTRL, 0, 7);
>> +static A9_COMP_GATE(vdin_meas, VDIN_MEAS_CLK_CTRL, 8, 0);
>> +
>> +static struct clk_regmap a9_vid_pll_div = {
>> + .data = &(struct meson_vid_pll_div_data){
>> + .val = {
>> + .reg_off = VID_PLL_CLK_DIV,
>> + .shift = 0,
>> + .width = 15,
>> + },
>> + .sel = {
>> + .reg_off = VID_PLL_CLK_DIV,
>> + .shift = 16,
>> + .width = 2,
>> + },
>> + },
>> + .hw.init = CLK_HW_INIT_FW_NAME("vid_pll_div", "hdmiout2",
>> + &meson_vid_pll_div_ro_ops, 0),
>> +};
>> +
>> +static struct clk_regmap a9_vid_pll_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = VID_PLL_CLK_DIV,
>> + .mask = 0x1,
>> + .shift = 18,
>> + },
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vid_pll_sel",
>> + ((const struct clk_parent_data []) {
>> + { .hw = &a9_vid_pll_div.hw },
>> + { .fw_name = "hdmiout2" }
>> + }), &clk_regmap_mux_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vid_pll = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_PLL_CLK_DIV,
>> + .bit_idx = 19,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vid_pll", &a9_vid_pll_sel.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vid_pll_vclk = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = HDMI_CLK_CTRL,
>> + .mask = 0x1,
>> + .shift = 15,
>> + },
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vid_pll_vclk",
>> + ((const struct clk_parent_data []) {
>> + { .hw = &a9_vid_pll.hw },
>> + { .fw_name = "hdmipix" }
>> + }), &clk_regmap_mux_ops, 0),
>> +};
>> +
>> +static const struct clk_parent_data a9_vclk_parents[] = {
>> + { .hw = &a9_vid_pll_vclk.hw },
>> + { .fw_name = "pix0", },
>> + { .fw_name = "vid1", },
>> + { .fw_name = "pix1", },
>> + { .fw_name = "fdiv3", },
>> + { .fw_name = "fdiv4", },
>> + { .fw_name = "fdiv5", },
>> + { .fw_name = "vid2", }
>> +};
>> +
>> +static struct clk_regmap a9_vclk_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = VID_CLK_CTRL,
>> + .mask = 0x7,
>> + .shift = 16,
>> + },
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vclk_sel", a9_vclk_parents,
>> + &clk_regmap_mux_ops, 0),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_in = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_DIV,
>> + .bit_idx = 16,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_in", &a9_vclk_sel.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_div = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = VID_CLK_DIV,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_div", &a9_vclk_in.hw,
>> + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL,
>> + .bit_idx = 19,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk", &a9_vclk_div.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_div1_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL,
>> + .bit_idx = 0,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_div1_en", &a9_vclk.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_div2_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL,
>> + .bit_idx = 1,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_div2_en", &a9_vclk.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
> Looks to me all this div_en / div repeating pattern would be easier to review
> with tiny macro .
Good point.
I tried to reduce the repeated div_en/div pattern using a helper macro.
It keeps the relationship between gate and fixed-factor clock more
compact and easier to review.
After using the helper macro, the div_en/div code can be simplified to
the following:
#define A9_VCLK(_name, _reg, _bit, _div, _parent) \
struct clk_regmap a9_##_name##_en = { \
.data = &(struct clk_regmap_gate_data){ \
.offset = _reg, \
.bit_idx = _bit, \
}, \
.hw.init = &(struct clk_init_data) { \
.name = #_name "_en", \
.ops = &clk_regmap_gate_ops, \
.parent_hws = (const struct clk_hw *[]) { _parent }, \
.num_parents = 1, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}; \
\
struct clk_fixed_factor a9_##_name = { \
.mult = 1, \
.div = _div, \
.hw.init = &(struct clk_init_data){ \
.name = #_name, \
.ops = &clk_fixed_factor_ops, \
.parent_hws = (const struct clk_hw *[]) { \
&a9_##_name##_en.hw \
}, \
.num_parents = 1, \
.flags = CLK_SET_RATE_PARENT, \
}, \
}; \
static A9_VCLK(vclk_div2, VID_CLK_CTRL, 1, 2, &a9_vclk.hw);
static A9_VCLK(vclk_div4, VID_CLK_CTRL, 2, 4, &a9_vclk.hw);
static A9_VCLK(vclk_div6, VID_CLK_CTRL, 3, 6, &a9_vclk.hw);
static A9_VCLK(vclk_div6, VID_CLK_CTRL, 4, 12, &a9_vclk.hw);
static A9_VCLK(vclk2_div2, VIID_CLK_CTRL, 1, 2, &a9_vclk2.hw);
static A9_VCLK(vclk2_div4, VIID_CLK_CTRL, 2, 4, &a9_vclk2.hw);
static A9_VCLK(vclk2_div6, VIID_CLK_CTRL, 3, 6, &a9_vclk2.hw);
static A9_VCLK(vclk2_div6, VIID_CLK_CTRL, 4, 12, &a9_vclk2.hw);
If you think splitting it further into separate helper macros would
improve readability.
I can do that as well.
>> +
>> +static struct clk_fixed_factor a9_vclk_div2 = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = CLK_HW_INIT_HW("vclk_div2", &a9_vclk_div2_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_div4_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL,
>> + .bit_idx = 2,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_div4_en", &a9_vclk.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk_div4 = {
>> + .mult = 1,
>> + .div = 4,
>> + .hw.init = CLK_HW_INIT_HW("vclk_div4", &a9_vclk_div4_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_div6_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL,
>> + .bit_idx = 3,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_div6_en", &a9_vclk.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk_div6 = {
>> + .mult = 1,
>> + .div = 6,
>> + .hw.init = CLK_HW_INIT_HW("vclk_div6", &a9_vclk_div6_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk_div12_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL,
>> + .bit_idx = 4,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk_div12_en", &a9_vclk.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk_div12 = {
>> + .mult = 1,
>> + .div = 12,
>> + .hw.init = CLK_HW_INIT_HW("vclk_div12", &a9_vclk_div12_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = VIID_CLK_CTRL,
>> + .mask = 0x7,
>> + .shift = 16,
>> + },
>> + .hw.init = CLK_HW_INIT_PARENTS_DATA("vclk2_sel", a9_vclk_parents,
>> + &clk_regmap_mux_ops, 0),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_in = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_DIV,
>> + .bit_idx = 16,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_in", &a9_vclk2_sel.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_div = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = VIID_CLK_DIV,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div", &a9_vclk2_in.hw,
>> + &clk_regmap_divider_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_CTRL,
>> + .bit_idx = 19,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2", &a9_vclk2_div.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_div1_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_CTRL,
>> + .bit_idx = 0,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div1_en", &a9_vclk2.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_div2_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_CTRL,
>> + .bit_idx = 1,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div2_en", &a9_vclk2.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk2_div2 = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div2", &a9_vclk2_div2_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_div4_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_CTRL,
>> + .bit_idx = 2,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div4_en", &a9_vclk2.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk2_div4 = {
>> + .mult = 1,
>> + .div = 4,
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div4", &a9_vclk2_div4_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_div6_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_CTRL,
>> + .bit_idx = 3,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div6_en", &a9_vclk2.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk2_div6 = {
>> + .mult = 1,
>> + .div = 6,
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div6", &a9_vclk2_div6_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_vclk2_div12_en = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VIID_CLK_CTRL,
>> + .bit_idx = 4,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div12_en", &a9_vclk2.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_fixed_factor a9_vclk2_div12 = {
>> + .mult = 1,
>> + .div = 12,
>> + .hw.init = CLK_HW_INIT_HW("vclk2_div12", &a9_vclk2_div12_en.hw,
>> + &clk_fixed_factor_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +/* Channel 5, 6 and 7 are unconnected */
>> +static u32 a9_vid_parents_val_table[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
>> +static const struct clk_hw *a9_vid_parents[] = {
>> + &a9_vclk_div1_en.hw,
>> + &a9_vclk_div2.hw,
>> + &a9_vclk_div4.hw,
>> + &a9_vclk_div6.hw,
>> + &a9_vclk_div12.hw,
>> + &a9_vclk2_div1_en.hw,
>> + &a9_vclk2_div2.hw,
>> + &a9_vclk2_div4.hw,
>> + &a9_vclk2_div6.hw,
>> + &a9_vclk2_div12.hw
>> +};
>> +
>> +static struct clk_regmap a9_vdac_sel = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = VIID_CLK_DIV,
>> + .mask = 0xf,
>> + .shift = 28,
>> + .table = a9_vid_parents_val_table,
>> + },
>> + .hw.init = CLK_HW_INIT_PARENTS_HW("vdac_sel", a9_vid_parents
>> + , &clk_regmap_mux_ops, 0),
>> +};
>> +
>> +static struct clk_regmap a9_vdac = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL2,
>> + .bit_idx = 4,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("vdac", &a9_vdac_sel.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
>> +static struct clk_regmap a9_enc_sel = {
> Should this be enc0 then ? for consistency ?
> Same applies to similar instance (it is the same discussion we already
> had on the T7 I believe)
Yes, that makes sense.
I'll rename them to a9_encoder0 and a9_encoder1 for consistency, and
I'll check for other similar instances as well.
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = VIID_CLK_DIV,
>> + .mask = 0xf,
>> + .shift = 12,
>> + .table = a9_vid_parents_val_table,
>> + },
>> + .hw.init = CLK_HW_INIT_PARENTS_HW("enc_sel", a9_vid_parents
>> + , &clk_regmap_mux_ops, 0),
>> +};
>> +
>> +static struct clk_regmap a9_enc = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = VID_CLK_CTRL2,
>> + .bit_idx = 10,
>> + },
>> + .hw.init = CLK_HW_INIT_HW("enc", &a9_enc_sel.hw,
>> + &clk_regmap_gate_ops, CLK_SET_RATE_PARENT),
>> +};
>> +
[ ... ]
> --
> Jerome
--
Jian
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