[PATCH] ARM: disable broken eBPF JIT on the Risc PC

[David Laight]

On Sun, 14 Jun 2026 14:44:38 -0700
Ethan Nelson-Moore <enelsonmoore at gmail.com> wrote:

> Hi, David,
> 
> On Sun, Jun 14, 2026 at 4:58 AM David Laight
> <david.laight.linux at gmail.com> wrote:
> > Isn't it more the case that the ldrh/strh instructions were added for armv4.
> > Whether the bus supports 16bit accesses is entirely different.  
> 
> No, it is in fact the bus. While the Risc PC initially shipped with
> ARMv3 CPUs, which the kernel no longer supports, it was later upgraded
> to an ARMv4 StrongARM CPU. However, its bus was designed for ARMv3
> CPUs and has no way to represent a half-word access to memory. This
> means that ldrh/strh will execute (because the CPU supports them) but
> do not function as intended.

Ok, so they work fine for cached accesses.
The only issue will be with uncached ones?
(Or do I remember the strongarm having a write-through cache?)

It just seems odd because byte writes are usually handled with four
byte-enable lines; so the targets support all 16 combinations even
though a cpu will (normally) only be able to generate 8 of them.

	David

> 
> Ethan