[PATCH] ARM: disable broken eBPF JIT on the Risc PC

[David Laight]

On Sun, 17 May 2026 18:49:17 -0700
Ethan Nelson-Moore <enelsonmoore at gmail.com> wrote:

> The eBPF JIT unconditionally generates ldrh/strh instructions, which do
> not function correctly on the Risc PC because its bus is unable to
> signal half-word accesses. Work around this issue by disabling the eBPF
> JIT when building for ARMv3 (the Risc PC is the only currently
> supported ARMv3 machine).

Isn't it more the case that the ldrh/strh instructions were added for armv4.
Whether the bus supports 16bit accesses is entirely different.

I'm guessing that WRITE_ONCE() gets implemented as two 8-bit writes and
the code 'just hopes' than an ISR won't care and won't do an update.

	David

> 
> Fixes: 39c13c204bb1 ("arm: eBPF JIT compiler")
> Cc: stable at vger.kernel.org
> Signed-off-by: Ethan Nelson-Moore <enelsonmoore at gmail.com>
> ---
>  arch/arm/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1155c78bb6aa..8185d013e5d1 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -98,7 +98,7 @@ config ARM
>  	select HAVE_ARCH_TRACEHOOK
>  	select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
>  	select HAVE_ARM_SMCCC if CPU_V7
> -	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
> +	select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 && !CPU_32v3
>  	select HAVE_CONTEXT_TRACKING_USER
>  	select HAVE_C_RECORDMCOUNT
>  	select HAVE_BUILDTIME_MCOUNT_SORT