[Question] Enabling CoreSight TRBE in firmware on CIX Orion O6

[Yunseong Kim]

Hi,

> On Wed, Jun 10, 2026 at 03:42:25PM +0800, Gary Yang wrote:
> 
> [...]
> 
>>>   (2) Or expose the full CoreSight topology in ACPI:
>>>      - Add ARMHC97C (TMC-ETR) device with MMIO base address
>>>      - Add ARMHC502 (funnel) devices if applicable
>>>      - Reference: ARM DEN0067 (CoreSight Architecture ACPI bindings)
> 
> The CPUs on O6 support ETE + TRBE, you don't need to use ETR or funnel
> modules.
> 
>> The firmware (TF-A) for the Radxa O6 is provided and maintained by Radxa. We 
>> will forward your request to the Radxa firmware team and ask them to evaluate 
>> enabling TRBE access from non-secure EL1/EL2 (i.e. setting MDCR_EL3.NSTBE = 1 
>> in TF-A), as you suggested.
> 
> The issue is caused by ACPI: the APIC table does not contain a TRBE
> interrupt, and the SSDT is missing ETE nodes (ETE node should be
> present for each CPU):
> 
>   Device (CPU0)
>   {
>     ...
> 
>     Device ( ETE0 ) {
>         Name (_UID, Zero)
>         Name (_HID , "ARMHC500")
>     }
>   }
> 
> Thanks,
> Leo


Thanks, Gary and Leo.                                                                           

I'm looking forward to adding arm64 CoreSight usage on CIX Orion O6 board.

If the board supports CoreSight, I'll make sure to write on the perf tools Wiki:

  https://perf.wiki.kernel.org/index.php/Main_Page

Best regards,
Yunseong