[PATCH v3 3/5] dt-bindings: clock: cix,sky1-audss-clock: add audss clock controller
Krzysztof Kozlowski
krzk at kernel.org
Thu Jun 11 00:42:20 PDT 2026
On Wed, Jun 10, 2026 at 03:56:43PM +0800, joakim.zhang at cixtech.com wrote:
> + '#clock-cells':
> + const: 1
> + description:
> + Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss.h.
> +
> + clocks:
> + items:
> + - description: I2S parent clock for sampling rates multiple of 8kHz.
> + - description: I2S parent clock for sampling rates multiple of 11.025kHz.
> + - description: clock feeding most devices in audss (NOC, DSP, SRAM, HDA, DMAC, I2S, and Mailbox).
> + - description: clock feeding for HDA, Timer and Watchdog, which is a delicated 48MHz clock.
> +
> + clock-names:
> + items:
> + - const: x8k
> + - const: x11k
> + - const: sys
> + - const: 48m
> +
> + resets:
> + maxItems: 1
> + description: Audio subsystem NoC (or bus) reset line.
> +
> + power-domains:
> + maxItems: 1
> + description: Audio subsystem power domain.
Same comments as last time, but let's keep discussion in previous patch.
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - clocks
> + - clock-names
> + - resets
> + - power-domains
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/cix,sky1.h>
> +
> + clock-controller {
> + compatible = "cix,sky1-audss-clock";
> + power-domains = <&smc_devpd 0>;
> + #clock-cells = <1>;
> + clocks = <&scmi_clk CLK_TREE_AUDIO_CLK0>, <&scmi_clk CLK_TREE_AUDIO_CLK2>,
> + <&scmi_clk CLK_TREE_AUDIO_CLK4>, <&scmi_clk CLK_TREE_AUDIO_CLK5>;
> + clock-names = "x8k", "x11k", "sys", "48m";
> + resets = <&s5_syscon 31>;
> + };
> diff --git a/include/dt-bindings/clock/cix,sky1-audss.h b/include/dt-bindings/clock/cix,sky1-audss.h
> new file mode 100644
> index 000000000000..033046407dee
> --- /dev/null
> +++ b/include/dt-bindings/clock/cix,sky1-audss.h
Filename must match the compatible.
Best regards,
Krzysztof
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