[PATCH 3/3] arm64: dts: cortina-access: Add DTS for CA8289 SoC and Venus board

[Krzysztof Kozlowski]

On 10/06/2026 13:28, Jason Li wrote:
> Add SoC DTSI for the Cortina-Access CA8289 (Venus) and a board DTS for
> the Venus engineering board. The description covers the minimum set of
> hardware nodes needed to boot a kernel with an INITRD rootfs: CPUs,
> GIC, timer, PSCI, fixed clock and UART.
> 
> Signed-off-by: Jason Li <jason.li at cortina-access.com>
> Assisted-by: Claude:claude-opus-4-8

SoB should be the last tag.

Also, it does not match From field.

> ---
>  MAINTAINERS                                   |   1 +
>  arch/arm64/Kconfig.platforms                  |  10 ++
>  arch/arm64/boot/dts/Makefile                  |   1 +
>  arch/arm64/boot/dts/cortina-access/Makefile   |   2 +
>  .../dts/cortina-access/ca8289-engboard.dts    |  31 +++++
>  .../boot/dts/cortina-access/ca8289-soc.dtsi   | 118 ++++++++++++++++++
>  6 files changed, 163 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/cortina-access/Makefile
>  create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
>  create mode 100644 arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 515d89d96472..ebfdb9c267cc 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2826,6 +2826,7 @@ L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/arm/cortina-access.yaml
>  F:	Documentation/devicetree/bindings/serial/cortina-access,serial.yaml
> +F:	arch/arm64/boot/dts/cortina-access/
>  
>  ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
>  M:	Hans Ulli Kroll <ulli.kroll at googlemail.com>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index dc995a732117..ba6dda0660c3 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -134,6 +134,16 @@ config ARCH_CIX
>  	  This enables support for the Cixtech SoC family,
>  	  like P1(sky1).
>  
> +config ARCH_CORTINA_ACCESS
> +	bool "Cortina-Access SoC Family"
> +	select GPIOLIB
> +	select PINCTRL
> +	help
> +	  This enables support for Cortina-Access SoCs.  The family
> +	  includes ARMv8-based devices targeting networking and access
> +	  applications.
> +	  If you have a Cortina-Access board, say Y here.
> +
>  config ARCH_EXYNOS
>  	bool "Samsung Exynos SoC family"
>  	select COMMON_CLK_SAMSUNG
> diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
> index 98ec8f1b76e4..a599f525fb9a 100644
> --- a/arch/arm64/boot/dts/Makefile
> +++ b/arch/arm64/boot/dts/Makefile
> @@ -16,6 +16,7 @@ subdir-y += broadcom
>  subdir-y += bst
>  subdir-y += cavium
>  subdir-y += cix
> +subdir-y += cortina-access
>  subdir-y += exynos
>  subdir-y += freescale
>  subdir-y += hisilicon
> diff --git a/arch/arm64/boot/dts/cortina-access/Makefile b/arch/arm64/boot/dts/cortina-access/Makefile
> new file mode 100644
> index 000000000000..554893f381fe
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cortina-access/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_CORTINA_ACCESS) += ca8289-engboard.dtb
> diff --git a/arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts b/arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
> new file mode 100644
> index 000000000000..c8289a0f8269
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cortina-access/ca8289-engboard.dts
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Cortina Access Venus Engineering Board
> + *
> + * Copyright (C) 2026, Cortina Access Inc.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "ca8289-soc.dtsi"
> +
> +/ {
> +	model = "Cortina Access Venus Engineering Board";
> +	compatible = "cortina-access,ca8289-engboard";
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory at 0 {	/* 512MB */
> +		device_type = "memory";
> +		reg = <0x00000000 0x00000000 0x0 0x20000000>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> new file mode 100644
> index 000000000000..8e7ffcf4ccab
> --- /dev/null
> +++ b/arch/arm64/boot/dts/cortina-access/ca8289-soc.dtsi
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * dts file for Cortina Access CA8289 SoC
> + *
> + * Copyright (C) 2026, Cortina Access Inc.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu at 0 {
> +			compatible = "arm,cortex-a55", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +		};

Missing blank lines. Look at existing code how this is supposed to look
like.

> +		cpu1: cpu at 100 {
> +			compatible = "arm,cortex-a55", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x0 0x100>;
> +			enable-method = "psci";
> +		};
> +		cpu2: cpu at 200 {
> +			compatible = "arm,cortex-a55", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x0 0x200>;
> +			enable-method = "psci";
> +		};
> +		cpu3: cpu at 300 {
> +			compatible = "arm,cortex-a55", "arm,armv8";
> +			device_type = "cpu";
> +			reg = <0x0 0x300>;
> +			enable-method = "psci";
> +		};
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	gic: interrupt-controller at 4f8000000 {

And now you repeat basic mistakes:
1. Pointed out by W=1 dtbs_check build
2. Fixed long time in every source
3. Explicitly documented in writing bindings and DTS coding style


> +		compatible = "arm,gic-v3";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		#redistributor-regions = <1>;
> +		reg = <0x00000004 0xF8000000 0 0x10000>,
> +		      <0x00000004 0xF8040000 0 0x80000>;

Read DTS coding style.

> +	};
> +
> +	apb_pclk: apb-pclk {

Nope, drop entire node.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <125000000>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		/* TrustZone reserved region; must not be mapped by the kernel */
> +		tz_pool: tz-buffer at f000000 {
> +			reg = <0x0 0x0F000000 0x0 0x1000000>;
> +			no-map;
> +		};
> +	};
> +
> +	/* See Documentation/devicetree/bindings/timer/arm,arch_timer.yaml */
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +		clock-frequency = <25000000>;
> +	};
> +
> +	uart0: serial at f4329188 {
> +		device_type = "serial";
> +		compatible = "cortina-access,serial";
> +		reg = <0x00000000 0xf4329188 0x0 0x30>;

This is AI slop. Whatever Claude convinced you to do, it is nothing like
upstream kernel source.

Best regards,
Krzysztof