[PATCH] arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap

[Josua Mayer]

A 3GB non-prefetchable PCIe bus window can overlap with inbound DMA
addresses for low system RAM, so DMA transactions may be routed to a BAR
on the same host bridge instead of memory.

Change the 32-bit non-prefetchable PCIe window back from 3GB to 1GB on all
controllers, avoiding that overlap while keeping the added 64-bit
prefetchable region.

This partially reverts commit 9ed301397090 ("arm64: dts: lx2160a-rev2:
extend 32-bit and add 64-bit pci regions").

Fixes: 9ed301397090 ("arm64: dts: lx2160a-rev2: extend 32-bit and add 64-bit pci regions")
Reported-by: Arnd Bergmann <arnd at arndb.de>
Closes: https://lore.kernel.org/r/9e6326f6-dad1-4169-a63c-e62ee5b341f2@app.fastmail.com
Signed-off-by: Josua Mayer <josua at solid-run.com>
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
index 3570399f9b21c..3d2637fee2d35 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi
@@ -17,7 +17,7 @@ &pcie1 {
 	ranges = /* 16-Bit IO Window */
 		 <0x81000000 0x00 0x00000000 0x80 0x00010000 0x00 0x00010000>,
 		 /* 32-Bit - non-prefetchable */
-		 <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0xc0000000>,
+		 <0x82000000 0x00 0x40000000 0x80 0x40000000 0x00 0x40000000>,
 		 /* 64-Bit - prefetchable - 16GB */
 		 <0xC3000000 0x84 0x00000000 0x84 0x00000000 0x04 0x00000000>;
 
@@ -37,7 +37,7 @@ &pcie2 {
 	ranges = /* 16-Bit IO Window */
 		 <0x81000000 0x00 0x00000000 0x88 0x00010000 0x00 0x00010000>,
 		 /* 32-Bit - non-prefetchable */
-		 <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0xc0000000>,
+		 <0x82000000 0x00 0x40000000 0x88 0x40000000 0x00 0x40000000>,
 		 /* 64-Bit - prefetchable - 16GB */
 		 <0xC3000000 0x8c 0x00000000 0x8c 0x00000000 0x04 0x00000000>;
 
@@ -57,7 +57,7 @@ &pcie3 {
 	ranges = /* 16-Bit IO Window */
 		 <0x81000000 0x00 0x00000000 0x90 0x00010000 0x00 0x00010000>,
 		 /* 32-Bit - non-prefetchable */
-		 <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0xc0000000>,
+		 <0x82000000 0x00 0x40000000 0x90 0x40000000 0x00 0x40000000>,
 		 /* 64-Bit - prefetchable - 16GB */
 		 <0xC3000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>;
 
@@ -78,7 +78,7 @@ &pcie4 {
 	ranges = /* 16-Bit IO Window */
 		 <0x81000000 0x00 0x00000000 0x98 0x00010000 0x00 0x00010000>,
 		 /* 32-Bit - non-prefetchable */
-		 <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0xc0000000>,
+		 <0x82000000 0x00 0x40000000 0x98 0x40000000 0x00 0x40000000>,
 		 /* 64-Bit - prefetchable - 16GB */
 		 <0xC3000000 0x9c 0x00000000 0x9c 0x00000000 0x04 0x00000000>;
 
@@ -98,7 +98,7 @@ &pcie5 {
 	ranges = /* 16-Bit IO Window */
 		 <0x81000000 0x00 0x00000000 0xa0 0x00010000 0x00 0x00010000>,
 		 /* 32-Bit - non-prefetchable */
-		 <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0xc0000000>,
+		 <0x82000000 0x00 0x40000000 0xa0 0x40000000 0x00 0x40000000>,
 		 /* 64-Bit - prefetchable - 16GB */
 		 <0xC3000000 0xa4 0x00000000 0xa4 0x00000000 0x04 0x00000000>;
 
@@ -118,7 +118,7 @@ &pcie6 {
 	ranges = /* 16-Bit IO Window */
 		 <0x81000000 0x00 0x00000000 0xa8 0x00010000 0x00 0x00010000>,
 		 /* 32-Bit - non-prefetchable */
-		 <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0xc0000000>,
+		 <0x82000000 0x00 0x40000000 0xa8 0x40000000 0x00 0x40000000>,
 		 /* 64-Bit - prefetchable - 16GB */
 		 <0xC3000000 0xac 0x00000000 0xac 0x00000000 0x04 0x00000000>;
 

---
base-commit: c10cfc952215644956284a42fa7b7860dfbcb5f5
change-id: 20260610-lx2160-pcie-fix-ranges-32bit-0868570e495f

Best regards,
-- 
Josua Mayer <josua at solid-run.com>