[GIT PULL] ARM: mvebu: dt64 for v7.2 (#1)

[Arnd Bergmann]

On Fri, Jun 5, 2026, at 17:20, Gregory CLEMENT wrote:
>
> ----------------------------------------------------------------
> mvebu dt64 for 7.2 (part 1)
>
> Mark EIP97 as dma-coherent for Armada 3720
>
> ----------------------------------------------------------------
> Aleksander Jan Bajkowski (1):
>       arm64: dts: marvell: armada-37xx: mark EIP97 as dma-coherent

Hi Gregory and Aleksander,

I'm a bit surprised by this oneline change. Since you successfully tested
this, I assume the change is correct, but I have two questions that
I would like to have an answer for before I pull it.

- I would expect a missing 'dma-coherent' property to cause data
  corruption, as the DMA master may write directly into the L2
  cache, which is then invalidated before the CPU accesses it.
  Do you have any idea how this one ends up working even when
  the property is missing?

- I see that the Product Brief for Armada 37xx mentions that it
  has a "High-bandwidth, low-latency IO Cache Coherency" interconnect,
  which also indicates that the patch is correct. However I don't
  see why it's only the crypto engine that needs it. What about
  the other high-speed DMA masters (neta, xhci, pcie, sata, ...)?

       Arnd