[PATCH v4 4/5] phy: fsl-imx8mq-usb: add control register regmap

[Xu Yang]

On Fri, Jun 05, 2026 at 11:28:50AM -0400, Frank Li wrote:
> On Fri, Jun 05, 2026 at 07:13:05PM +0800, Xu Yang wrote:
> > From: Xu Yang <xu.yang_2 at nxp.com>
> >
> > The CR port is a simple 16-bit data/address parallel port that is
> > accessed through 32-bit MMIO registers for on-chip access to the
> > control registers inside the USB 3.0 femtoPHY. Add control register
> > regmap and export these registers by debugfs to help PHY's diagnostic.
> >
> > Signed-off-by: Xu Yang <xu.yang_2 at nxp.com>
> >
> 
> Reviewed-by: Frank Li <Frank.Li at nxp.com>
> 
> > ---
> > Changes in v4:
> >  - improve commit message as Haibo's suggestion
> > Changes in v3:
> >  - drop Frank's tag because it includes other changes
> >  - new patch
> > ---
> >  drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 27 ++++++++++++++++++++++++++-
> >  1 file changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
> > index 27aa696f5dd4..e24f46d7924b 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
> > @@ -1,5 +1,5 @@
> >  // SPDX-License-Identifier: GPL-2.0+
> > -/* Copyright (c) 2017 NXP. */
> > +/* Copyright 2017-2026 NXP. */
> >
> >  #include <linux/bitfield.h>
> >  #include <linux/clk.h>
> > @@ -11,6 +11,7 @@
> >  #include <linux/platform_device.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/regulator/consumer.h>
> > +#include <linux/regmap.h>
> >  #include <linux/usb/typec_mux.h>
> >
> >  #define PHY_CTRL0			0x0
> > @@ -56,6 +57,8 @@
> >  #define PHY_CTRL6_ALT_CLK_EN		BIT(1)
> >  #define PHY_CTRL6_ALT_CLK_SEL		BIT(0)
> >
> > +#define PHY_CRCTL			0x30
> > +
> >  #define PHY_TUNE_DEFAULT		0xffffffff
> >
> >  #define TCA_CLK_RST			0x00
> > @@ -119,6 +122,7 @@ struct imx8mq_usb_phy {
> >  	void __iomem *base;
> >  	struct regulator *vbus;
> >  	struct tca_blk *tca;
> > +	struct regmap *cr_regmap;
> >  	u32 pcs_tx_swing_full;
> >  	u32 pcs_tx_deemph_3p5db;
> >  	u32 tx_vref_tune;
> > @@ -667,6 +671,14 @@ static const struct of_device_id imx8mq_usb_phy_of_match[] = {
> >  };
> >  MODULE_DEVICE_TABLE(of, imx8mq_usb_phy_of_match);
> >
> > +static const struct regmap_config imx_cr_regmap_config = {
> > +	.name = "cr",
> > +	.reg_bits = 32,
> > +	.val_bits = 32,
> > +	.reg_stride = 4,
> > +	.max_register = 0x7,
> > +};
> > +
> >  static int imx8mq_usb_phy_probe(struct platform_device *pdev)
> >  {
> >  	struct phy_provider *phy_provider;
> > @@ -696,6 +708,13 @@ static int imx8mq_usb_phy_probe(struct platform_device *pdev)
> >  	if (IS_ERR(imx_phy->base))
> >  		return PTR_ERR(imx_phy->base);
> >
> > +	imx_phy->cr_regmap = devm_regmap_init_mmio(dev, imx_phy->base + PHY_CRCTL,
> > +						   &imx_cr_regmap_config);
> > +	if (IS_ERR(imx_phy->cr_regmap)) {
> > +		dev_warn(dev, "Fail to init debug register regmap\n");
> > +		imx_phy->cr_regmap = NULL;
> > +	}
> > +
> >  	ret = devm_pm_runtime_set_active_enabled(dev);
> >  	if (ret)
> >  		return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
> > @@ -731,6 +750,9 @@ static int imx8mq_usb_phy_runtime_suspend(struct device *dev)
> >  {
> >  	struct imx8mq_usb_phy *imx_phy = dev_get_drvdata(dev);
> >
> > +	if (imx_phy->cr_regmap)
> > +		regcache_cache_only(imx_phy->cr_regmap, true);
> > +
> 
> I think this common problem, is possible to change
> regmap_read_debugfs(), let it call runtime_pm_get(), there are already
> have runtime_pm in regmap field.
 
Yes, it should be a common issue when access debugfs on a suspended device.
Not sure why regmap common driver doesn't add it. We can do it in future if
more such cases appear.

> 
> So you debug fs always to get update value, instead cached value?

The default cache type is REGCACHE_NONE in imx_cr_regmap_config. So no
cache at all. The main purpose is to block register access here. Once
cache_only is disabled, it will read HW register value.

Thanks,
Xu Yang