[PATCH v5 1/3] dt-bindings: imx6q-pcie: Add optional interrupt entries for intr, aer and pme

[Hongxing Zhu]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk at kernel.org>
> Sent: Sunday, May 31, 2026 7:47 PM
> To: Hongxing Zhu <hongxing.zhu at nxp.com>
> Cc: robh at kernel.org; krzk+dt at kernel.org; conor+dt at kernel.org;
> bhelgaas at google.com; Frank Li <frank.li at nxp.com>; l.stach at pengutronix.de;
> lpieralisi at kernel.org; kwilczynski at kernel.org; mani at kernel.org;
> s.hauer at pengutronix.de; kernel at pengutronix.de; festevam at gmail.com; linux-
> pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> devicetree at vger.kernel.org; imx at lists.linux.dev; linux-kernel at vger.kernel.org
> Subject: Re: [PATCH v5 1/3] dt-bindings: imx6q-pcie: Add optional interrupt
> entries for intr, aer and pme
> 
> On Thu, May 21, 2026 at 05:32:53PM +0800, Richard Zhu wrote:
> > The i.MX95 PCIe controller introduces three dedicated hardware
> > interrupt
> > lines:
> > - intr: general controller events
> > - aer: Advanced Error Reporting
> > - pme: Power Management Events
> >
> > Earlier i.MX PCIe variants (imx6q, imx6sx, imx6qp, imx7d, imx8mm,
> > imx8mp, imx8mq, imx8q) do not have these dedicated interrupt lines.
> >
> > PCIe basic functionality (enumeration, configuration, and data
> > transfer) works correctly regardless of whether these interrupts are
> > present. Mark these interrupts as optional to maintain backward
> > compatibility with SoCs that lack these hardware interrupt lines.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> > Reviewed-by: Frank Li <Frank.Li at nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index 9d1349855b42..cf709132ff1e 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -58,12 +58,18 @@ properties:
> >      items:
> >        - description: builtin MSI controller.
> >        - description: builtin DMA controller.
> > +      - description: PCIe event interrupt.
> > +      - description: builtin AER SPI standalone interrupt line.
> > +      - description: builtin PME SPI standalone interrupt line.
> 
> Same feedback as before, nothing improved. Schema says imx6q has these
> interrupts, commit msg says otherwise.
> 
> Please read entire binding - you would easily guess what is there to do.
> And you already received such comments.
Sorry, I didn't understand your previous feedback clearly.

I now realize the issue: the schema currently allows these three optional
interrupts for all compatible strings (including imx6q), but according to the
hardware specifications, only i.MX95 has these additional interrupts.

I will update the binding to use conditional constraints (if/then schema) to
specify that these three optional interrupts are only valid for the i.MX95
variant, while other variants like imx6q should not have them.

Thank you for your patience.

Best Regards
Richard Zhu
> 
> NAK