[PATCH 2/2] drm/rockchip: dsi: Add dphy_get_timing support for multiple PHY types

[Heiko Stuebner]

Am Dienstag, 24. März 2026, 09:58:38 Mitteleuropäische Sommerzeit schrieb Chaoyi Chen:
> From: Chaoyi Chen <chaoyi.chen at rock-chips.com>
> 
> Currently, there are generally two types of DPHY for Rockchip. One is
> the DPHY used by RK3288/RK3399, whose timing is described by Table A-3
> High-Speed Transition Times in the databook. The other is the DPHY used
> by PX30 and its successors. If its timing is still described using
> RK3288/RK3399, it may not perform correctly on some DSI panel.
> 
> Add dphy_get_timing for different D-PHY types to adapt to timing
> differences.
> 
> Signed-off-by: Chaoyi Chen <chaoyi.chen at rock-chips.com>
> ---
>  .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   | 45 ++++++++++++++++++-
>  1 file changed, 43 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index d3bacfae174e..2d1c9e54ff85 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -247,6 +247,7 @@ enum {
>  	BIASEXTR_127_7,
>  };
>  
> +struct dw_mipi_dsi_rockchip;
>  struct rockchip_dw_dsi_chip_data {
>  	u32 reg;
>  
> @@ -262,6 +263,9 @@ struct rockchip_dw_dsi_chip_data {
>  	u32 lanecfg2_grf_reg;
>  	u32 lanecfg2;
>  
> +	int (*dphy_get_timing)(struct dw_mipi_dsi_rockchip *dsi, unsigned int lane_mbps,
> +			       struct dw_mipi_dsi_dphy_timing *timing);
> +
>  	int (*dphy_rx_init)(struct phy *phy);
>  	int (*dphy_rx_power_on)(struct phy *phy);
>  	int (*dphy_rx_power_off)(struct phy *phy);
> @@ -721,8 +725,9 @@ static struct hstt hstt_table[] = {
>  };
>  
>  static int
> -dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> -			   struct dw_mipi_dsi_dphy_timing *timing)
> +dw_mipi_dsi_phy_rk3288_get_timing(struct dw_mipi_dsi_rockchip *dsi,
> +				  unsigned int lane_mbps,
> +				  struct dw_mipi_dsi_dphy_timing *timing)
>  {
>  	int i;
>  
> @@ -738,6 +743,32 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>  	return 0;
>  }
>  
> +static const struct dw_mipi_dsi_dphy_timing dphy_timing_px30 = {
> +	.clk_lp2hs = 0x40,
> +	.clk_hs2lp = 0x40,
> +	.data_lp2hs = 0x10,
> +	.data_hs2lp = 0x14,
> +};

so just to make sure, the timing on the px30 (and later) variant is the
same for all lane speeds?

Please include that bit in the commit description

Thanks
Heiko