[PATCH v3 1/2] arm64: cpufeature: Add WORKAROUND_DISABLE_CNP capability

[Vladimir Murzin]

On 6/1/26 12:19, Zeng Heng wrote:
> From: Zeng Heng <zengheng4 at huawei.com>
> 
> The NVIDIA Carmel CNP erratum is not the only case requiring CNP to be
> disabled. Abstract this into a common WORKAROUND_DISABLE_CNP capability
> to facilitate adding errata for future chips and reduce duplicate
> checks in has_useable_cnp().
> 
> This serves as a prerequisite for the subsequent Hisilicon erratum
> 162100125.
> 
> Suggested-by: Vladimir Murzin <vladimir.murzin at arm.com>
> Signed-off-by: Zeng Heng <zengheng4 at huawei.com>
> ---
>  arch/arm64/Kconfig               | 4 ++++
>  arch/arm64/include/asm/cpucaps.h | 4 ++--
>  arch/arm64/kernel/cpu_errata.c   | 4 ++--
>  arch/arm64/kernel/cpufeature.c   | 2 +-
>  arch/arm64/tools/cpucaps         | 2 +-
>  5 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index fe60738e5943..f297517a83b9 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -1315,9 +1315,13 @@ config QCOM_FALKOR_ERRATUM_E1041
> 
>  	  If unsure, say Y.
> 
> +config ARM64_WORKAROUND_DISABLE_CNP
> +	bool
> +
>  config NVIDIA_CARMEL_CNP_ERRATUM
>  	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
>  	default y
> +	select ARM64_WORKAROUND_DISABLE_CNP
>  	help
>  	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
>  	  invalidate shared TLB entries installed by a different core, as it would
> diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
> index d0d3cdd5763c..25c61cda901c 100644
> --- a/arch/arm64/include/asm/cpucaps.h
> +++ b/arch/arm64/include/asm/cpucaps.h
> @@ -58,8 +58,8 @@ cpucap_is_possible(const unsigned int cap)
>  		return IS_ENABLED(CONFIG_ARM64_ERRATUM_2658417);
>  	case ARM64_WORKAROUND_CAVIUM_23154:
>  		return IS_ENABLED(CONFIG_CAVIUM_ERRATUM_23154);
> -	case ARM64_WORKAROUND_NVIDIA_CARMEL_CNP:
> -		return IS_ENABLED(CONFIG_NVIDIA_CARMEL_CNP_ERRATUM);
> +	case ARM64_WORKAROUND_DISABLE_CNP:
> +		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_DISABLE_CNP);
>  	case ARM64_WORKAROUND_REPEAT_TLBI:
>  		return IS_ENABLED(CONFIG_ARM64_WORKAROUND_REPEAT_TLBI);
>  	case ARM64_WORKAROUND_SPECULATIVE_SSBS:
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index 5377e4c2eba2..b0db946568b7 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -801,11 +801,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
>  				  1, 0),
>  	},
>  #endif
> -#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
> +#ifdef CONFIG_ARM64_WORKAROUND_DISABLE_CNP
>  	{
>  		/* NVIDIA Carmel */
>  		.desc = "NVIDIA Carmel CNP erratum",
> -		.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
> +		.capability = ARM64_WORKAROUND_DISABLE_CNP,
>  		ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
>  	},
>  #endif
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 6d53bb15cf7b..20c5f24f74a9 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1785,7 +1785,7 @@ has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
>  	if (is_kdump_kernel())
>  		return false;
> 
> -	if (cpus_have_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
> +	if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP))
>  		return false;
> 
>  	return has_cpuid_feature(entry, scope);
> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
> index 811c2479e82d..9b85a84f6fd4 100644
> --- a/arch/arm64/tools/cpucaps
> +++ b/arch/arm64/tools/cpucaps
> @@ -120,7 +120,7 @@ WORKAROUND_CAVIUM_TX2_219_PRFM
>  WORKAROUND_CAVIUM_TX2_219_TVM
>  WORKAROUND_CLEAN_CACHE
>  WORKAROUND_DEVICE_LOAD_ACQUIRE
> -WORKAROUND_NVIDIA_CARMEL_CNP
> +WORKAROUND_DISABLE_CNP
>  WORKAROUND_PMUV3_IMPDEF_TRAPS
>  WORKAROUND_QCOM_FALKOR_E1003
>  WORKAROUND_QCOM_ORYON_CNTVOFF
> --
> 2.43.0
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin at arm.com>