[PATCH v4 1/1] arm64: dts: s32g: add PWM support for s32g2 and s32g3

[Frank Li]

On Fri, May 29, 2026 at 09:34:36AM +0200, Khristine Andreea Barbulescu wrote:
> Add PWM0 and PWM1 for S32G2 and S32G3 SoCs
>
> Reviewed-by: Enric Balletbo i Serra <eballetb at redhat.com>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu at oss.nxp.com>
> ---

Please rebase to https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git/log/?h=imx/dt64

Frank

>  arch/arm64/boot/dts/freescale/s32g2.dtsi      | 28 ++++++-
>  arch/arm64/boot/dts/freescale/s32g3.dtsi      | 30 ++++++-
>  .../boot/dts/freescale/s32gxxxa-evb.dtsi      | 78 ++++++++++++++++++-
>  3 files changed, 133 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..907cf74e61f3 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
>   * NXP S32G2 SoC family
>   *
>   * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
>   */
>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -554,6 +554,19 @@ i2c2: i2c at 401ec000 {
>  			status = "disabled";
>  		};
>
> +		pwm0: pwm at 401f4000 {
> +			compatible = "nxp,s32g2-ftm-pwm";
> +			reg = <0x401f4000 0x1000>;
> +			#pwm-cells = <3>;
> +			clocks = <&clks 5>,
> +				 <&clks 6>,
> +				 <&clks 5>,
> +				 <&clks 5>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				      "ftm_fix", "ftm_cnt_clk_en";
> +			status = "disabled";
> +		};
> +
>  		swt4: watchdog at 40200000 {
>  			compatible = "nxp,s32g2-swt";
>  			reg = <0x40200000 0x1000>;
> @@ -717,6 +730,19 @@ i2c4: i2c at 402dc000 {
>  			status = "disabled";
>  		};
>
> +		pwm1: pwm at 402e4000 {
> +			compatible = "nxp,s32g2-ftm-pwm";
> +			reg = <0x402e4000 0x1000>;
> +			#pwm-cells = <3>;
> +			clocks = <&clks 7>,
> +				 <&clks 8>,
> +				 <&clks 7>,
> +				 <&clks 7>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				      "ftm_fix", "ftm_cnt_clk_en";
> +			status = "disabled";
> +		};
> +
>  		usdhc0: mmc at 402f0000 {
>  			compatible = "nxp,s32g2-usdhc";
>  			reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d..a4a9e21d1361 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
>   *
>   * Authors: Ghennadi Procopciuc <ghennadi.procopciuc at nxp.com>
>   *          Ciprian Costea <ciprianmarian.costea at nxp.com>
> @@ -617,6 +617,20 @@ i2c2: i2c at 401ec000 {
>  			status = "disabled";
>  		};
>
> +		pwm0: pwm at 401f4000 {
> +			compatible = "nxp,s32g3-ftm-pwm",
> +				     "nxp,s32g2-ftm-pwm";
> +			reg = <0x401f4000 0x1000>;
> +			#pwm-cells = <3>;
> +			clocks = <&clks 5>,
> +				 <&clks 6>,
> +				 <&clks 5>,
> +				 <&clks 5>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				      "ftm_fix", "ftm_cnt_clk_en";
> +			status = "disabled";
> +		};
> +
>  		swt4: watchdog at 40200000 {
>  			compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
>  			reg = <0x40200000 0x1000>;
> @@ -792,6 +806,20 @@ i2c4: i2c at 402dc000 {
>  			status = "disabled";
>  		};
>
> +		pwm1: pwm at 402e4000 {
> +			compatible = "nxp,s32g3-ftm-pwm",
> +				     "nxp,s32g2-ftm-pwm";
> +			reg = <0x402e4000 0x1000>;
> +			#pwm-cells = <3>;
> +			clocks = <&clks 7>,
> +				 <&clks 8>,
> +				 <&clks 7>,
> +				 <&clks 7>;
> +			clock-names = "ftm_sys", "ftm_ext",
> +				      "ftm_fix", "ftm_cnt_clk_en";
> +			status = "disabled";
> +		};
> +
>  		usdhc0: mmc at 402f0000 {
>  			compatible = "nxp,s32g3-usdhc",
>  				     "nxp,s32g2-usdhc";
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> index 803ff4531077..be7b645afa2d 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2024 NXP
> + * Copyright 2024, 2026 NXP
>   *
>   * Authors: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
>   *          Ghennadi Procopciuc <ghennadi.procopciuc at oss.nxp.com>
> @@ -245,6 +245,70 @@ dspi5-grp4 {
>  			bias-pull-up;
>  		};
>  	};
> +
> +	ftm0_pins: ftm0-pins {
> +		ftm0-grp0 {
> +			pinmux = <0x2912>;
> +		};
> +
> +		ftm0-grp1 {
> +			pinmux = <0x122>,
> +				 <0xb42>;
> +			output-enable;
> +			input-enable;
> +		};
> +
> +		ftm0-grp2 {
> +			pinmux = <0xb13>,
> +				 <0xb53>;
> +			output-enable;
> +			input-enable;
> +		};
> +
> +		ftm0-grp3 {
> +			pinmux = <0x2904>;
> +		};
> +
> +		ftm0-grp4 {
> +			pinmux = <0x2925>;
> +		};
> +
> +		ftm0-grp5 {
> +			pinmux = <0x2936>;
> +		};
> +	};
> +
> +	ftm1_pins: ftm1-pins {
> +		ftm1-grp0 {
> +			pinmux = <0x1d3>;
> +			output-enable;
> +			input-enable;
> +		};
> +
> +		ftm1-grp1 {
> +			pinmux = <0x29b4>;
> +		};
> +
> +		ftm1-grp2 {
> +			pinmux = <0x29c3>;
> +		};
> +
> +		ftm1-grp3 {
> +			pinmux = <0x1f4>;
> +			output-enable;
> +			input-enable;
> +		};
> +
> +		ftm1-grp4 {
> +			pinmux = <0x202>;
> +			output-enable;
> +			input-enable;
> +		};
> +
> +		ftm1-grp5 {
> +			pinmux = <0x29d2>;
> +		};
> +	};
>  };
>
>  &can0 {
> @@ -293,6 +357,18 @@ &i2c4 {
>  	status = "okay";
>  };
>
> +&pwm0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&ftm0_pins>;
> +	status = "okay";
> +};
> +
> +&pwm1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&ftm1_pins>;
> +	status = "okay";
> +};
> +
>  &spi1 {
>  	pinctrl-0 = <&dspi1_pins>;
>  	pinctrl-names = "default";
> --
> 2.34.1
>