[PATCH v3 1/2] arm64: dts: imx8mq-evk: Enable MIPI CSI and dual OV5640 cameras
Kieran Bingham
kieran.bingham at ideasonboard.com
Mon Jun 1 04:20:22 PDT 2026
Quoting Robby Cai (2026-05-29 14:23:33)
> Enable the MIPI CSI-2 host controllers and CSI bridges, and add two
> OV5640 sensors on I2C1 and I2C2, forming two media pipelines:
>
> - OV5640 (I2C2) -> MIPI CSI1 -> CSI1 bridge
> - OV5640 (I2C1) -> MIPI CSI2 -> CSI2 bridge
>
> On the i.MX8MQ EVK, both sensors share a single reset GPIO line,
> while each sensor has an independent powerdown (PWDN) GPIO.
>
> Both sensors also share the same MCLK source (CLKO2), configured
> identically as required by the hardware design.
Shouldn't these be overlays? Does *every* IMX8MQ-EVK always have 2 x
OV5640 modules attached? And never anything else ?
--
Regards
Kieran
>
> Signed-off-by: Robby Cai <robby.cai at nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 150 +++++++++++++++++++
> 1 file changed, 150 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index d48f901487d4..7ff1a763890a 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -6,6 +6,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/media/video-interfaces.h>
> #include "imx8mq.dtsi"
>
> / {
> @@ -50,6 +51,20 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 {
> enable-active-high;
> };
>
> + reg_1v5: regulator-1v5 {
> + compatible = "regulator-fixed";
> + regulator-name = "DVDD_1V5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + };
> +
> + reg_2v8: regulator-2v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "AVDD_2V8";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> buck2_reg: regulator-buck2 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_buck2>;
> @@ -172,6 +187,14 @@ &A53_3 {
> cpu-supply = <&buck2_reg>;
> };
>
> +&csi1 {
> + status = "okay";
> +};
> +
> +&csi2 {
> + status = "okay";
> +};
> +
> &ddrc {
> operating-points-v2 = <&ddrc_opp_table>;
> status = "okay";
> @@ -330,12 +353,103 @@ vgen6_reg: vgen6 {
> };
> };
> };
> +
> + camera at 3c {
> + compatible = "ovti,ov5640";
> + reg = <0x3c>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_camera2_pwdn>;
> + clocks = <&clk IMX8MQ_CLK_CLKO2>;
> + clock-names = "xclk";
> + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
> + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
> + assigned-clock-rates = <20000000>;
> + powerdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
> + DOVDD-supply = <&sw4_reg>;
> + AVDD-supply = <®_2v8>;
> + DVDD-supply = <®_1v5>;
> +
> + port {
> + camera2_ep: endpoint {
> + remote-endpoint = <&mipi_csi2_in_ep>;
> + clock-lanes = <0>;
> + data-lanes = <1 2>;
> + };
> + };
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + camera at 3c {
> + compatible = "ovti,ov5640";
> + reg = <0x3c>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_camera1_pwdn>;
> + clocks = <&clk IMX8MQ_CLK_CLKO2>;
> + clock-names = "xclk";
> + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
> + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
> + assigned-clock-rates = <20000000>;
> + powerdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
> + DOVDD-supply = <&sw4_reg>;
> + AVDD-supply = <®_2v8>;
> + DVDD-supply = <®_1v5>;
> +
> + port {
> + camera1_ep: endpoint {
> + remote-endpoint = <&mipi_csi1_in_ep>;
> + clock-lanes = <0>;
> + data-lanes = <1 2>;
> + };
> + };
> + };
> };
>
> &lcdif {
> status = "okay";
> };
>
> +&mipi_csi1 {
> + assigned-clock-rates = <266000000>, <200000000>, <66000000>;
> + status = "okay";
> +
> + ports {
> + port at 0 {
> + reg = <0>;
> +
> + mipi_csi1_in_ep: endpoint {
> + remote-endpoint = <&camera1_ep>;
> + data-lanes = <1 2>;
> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> + };
> + };
> + };
> +};
> +
> +&mipi_csi2 {
> + assigned-clock-rates = <266000000>, <200000000>, <66000000>;
> + status = "okay";
> +
> + ports {
> + port at 0 {
> + reg = <0>;
> +
> + mipi_csi2_in_ep: endpoint {
> + remote-endpoint = <&camera2_ep>;
> + data-lanes = <1 2>;
> + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
> + };
> + };
> + };
> +};
> +
> &mipi_dsi {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -532,12 +646,34 @@ &wdog1 {
> };
>
> &iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_mclk>, <&pinctrl_camera_reset>;
> +
> pinctrl_buck2: vddarmgrp {
> fsl,pins = <
> MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
> >;
> };
>
> + pinctrl_camera1_pwdn: camera1pwdngrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
> + >;
> + };
> +
> + pinctrl_camera2_pwdn: camera2pwdngrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
> + >;
> + };
> +
> + /* Shared reset line for cameras on CSI1 and CSI2. */
> + pinctrl_camera_reset: cameraresetgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
> + >;
> + };
> +
> pinctrl_fec1: fec1grp {
> fsl,pins = <
> MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> @@ -565,12 +701,26 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
> >;
> };
>
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
> + >;
> + };
> +
> pinctrl_ir: irgrp {
> fsl,pins = <
> MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
> >;
> };
>
> + /* Shared MCLK for cameras on CSI1 and CSI2. */
> + pinctrl_mclk: mclkgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
> + >;
> + };
> +
> pinctrl_mipi_dsi: mipidsigrp {
> fsl,pins = <
> MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
> --
> 2.50.1
>
More information about the linux-arm-kernel
mailing list