[PATCH v2 1/2] iommu/arm-smmu-v3: Detect Tegra264 erratum

[Ashish Mhetre]

On 5/30/2026 3:00 AM, Nicolin Chen wrote:
> On Fri, May 29, 2026 at 02:08:29PM +0000, Ashish Mhetre wrote:
>> Tegra264 SMMU is affected by erratum where a TLB entry can survive an
>> invalidation that races with concurrent traffic targeting the same
>> entry. The hardware-recommended software workaround is to issue every
>> CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is
>> guaranteed to evict the entry. ATC_INV is not affected and must not be
>> doubled.
>>
>> The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot
>> be detected from hardware register. Tegra264 boots from device tree only
>> and has no ACPI/IORT support, so detection is through device tree only.
>>
>> Add the ARM_SMMU_OPT_TLBI_TWICE option and set it on instances matching
>> the existing "nvidia,tegra264-smmu" compatible. No callers consume the
>> option yet, next patch wires the workaround into the CMDQ issue paths.
> I was told to avoid "patch": once a patch is applied it becomes
> a commit. So, maybe "a subsequent change will wire".

Sure, I'll update it in next version.

>> Signed-off-by: Ashish Mhetre <amhetre at nvidia.com>
> Reviewed-by: Nicolin Chen <nicolinc at nvidia.com>

Thanks Nicolin.