[PATCH v3] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability

[Hongxing Zhu (OSS)]

> -----Original Message-----
> From: Bjorn Helgaas <helgaas at kernel.org>
> Sent: Thursday, July 30, 2026 12:57 AM
> To: Hongxing Zhu (OSS) <hongxing.zhu at oss.nxp.com>
> Cc: Frank Li <frank.li at nxp.com>; l.stach at pengutronix.de; lpieralisi at kernel.org;
> kwilczynski at kernel.org; mani at kernel.org; robh at kernel.org;
> bhelgaas at google.com; s.hauer at pengutronix.de; kernel at pengutronix.de;
> festevam at gmail.com; linux-pci at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; imx at lists.linux.dev; linux-kernel at vger.kernel.org;
> Hongxing Zhu <hongxing.zhu at nxp.com>
> Subject: Re: [PATCH v3] PCI: imx6: Update MPLLB bandwidth to improve i.MX95
> Gen3 PCIe stability
> 
> On Tue, Jul 14, 2026 at 10:41:07AM +0800, hongxing.zhu at oss.nxp.com wrote:
> > From: Richard Zhu <hongxing.zhu at nxp.com>
> >
> > Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with
> > the default MPLLB_BANDWIDTH value. This margin degradation worsens
> > across voltage and temperature (VT) variations and different test
> > matrices, potentially causing link stability issues.
> 
> What does "bandwidth marginality" mean?  And what does it mean to observe it?
> I guess it must mean some measurable thing is close to being out of spec?
> 
Yes, your assumption is correct.

The MPLLB_BW_OVRD_IN register provides an override value for MPLLB_BW (MPLL
Bandwidth) parameter in the i.MX95 PCIe PHY.

The default MPLLB_BW value is 120. During Gen3 PCIe testing, this default
value showed insufficient bandwidth margin, with further degradation observed
across voltage and temperature (VT) variations. Based on IC designer
recommendations, updating this value from 120 to 140 (0x8c) significantly
improves bandwidth margins across all VT conditions and test scenarios,
ensuring stable PCIe link operation.

> > Testing with MPLLB_BANDWIDTH value of 140 (0x8c) shows significant
> > improvement in bandwidth margins across all VT conditions and test
> > scenarios.
> >
> > Implement PHY register write helper function and configure:
> > - MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
> > - MPLLB_BW_OVRD_EN to enable the override
> 
> AFAICT we don't know what MPLLB_BW_OVRD_IN was before, so we don't know
> whether this increases or decreases the value.  And we don't really even know
> what MPLLB_BW_OVRD_IN specifies.
> 
This patch increases the MPLLB_BW value from its default of 120 to 140 as
recommended by the IC designers.

Best Regards
Richard Zhu
> > This ensures robust PCIe Gen3 performance across all operating
> > conditions.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu at nxp.com>
> > ---
> > Changes in v3:
> > Regarding Frank's comments, refine naming consistency and clarity.
> >
> > Changes in v2:
> > Update the register name and bit definitions.
> > Don't move IMX95_PCIE_PHY_CR_PARA_SEL settings.
> > ---
> >  drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++++++++++++++++++
> >  1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 53f3da6ab30d5..fadf14de10f7c 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -80,6 +80,17 @@
> >  #define IMX95_SID_MASK				GENMASK(5, 0)
> >  #define IMX95_MAX_LUT				32
> >
> > +#define IMX95_PCIE_PHY_REG_ADDR			0x3008
> > +#define IMX95_PCIE_PHY_REG_EN			BIT(31)
> > +#define IMX95_PCIE_PHY_REG_ADDR_MASK		GENMASK(15, 0)
> > +#define IMX95_PCIE_PHY_REG_DATA			0x300c
> > +#define IMX95_PCIE_PHY_MPLLB_OVRD_IN		0x2004
> > +/* BIT(10): Override enable for mpllb_bandwidth[15:0] */
> > +#define IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN		0x400
> > +/* Register offset: Override value for mpllb_bandwidth[15:0] */
> > +#define IMX95_PCIE_PHY_MPLLB_BW_IN		0x2005
> > +#define IMX95_PCIE_PHY_MPLLB_BW_VAL		0x8c
> > +
> >  #define IMX95_PCIE_RST_CTRL			0x3010
> >  #define IMX95_PCIE_COLD_RST			BIT(0)
> >
> > @@ -269,6 +280,16 @@ static int imx95_pcie_select_ref_clk_src(struct
> imx_pcie *imx_pcie)
> >  	return 0;
> >  }
> >
> > +static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr,
> > +u16 data) {
> > +	udelay(200);
> > +	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_REG_ADDR,
> > +			   IMX95_PCIE_PHY_REG_EN,
> IMX95_PCIE_PHY_REG_EN);
> > +	regmap_update_bits(imx_pcie->iomuxc_gpr,
> IMX95_PCIE_PHY_REG_ADDR,
> > +			   IMX95_PCIE_PHY_REG_ADDR_MASK, addr);
> > +	regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA,
> data); }
> > +
> >  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)  {
> >  	/*
> > @@ -289,6 +310,11 @@ static int imx95_pcie_init_phy(struct imx_pcie
> *imx_pcie)
> >  			IMX95_PCIE_PHY_CR_PARA_SEL,
> >  			IMX95_PCIE_PHY_CR_PARA_SEL);
> >
> > +	imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_BW_IN,
> > +			     IMX95_PCIE_PHY_MPLLB_BW_VAL);
> > +	imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_OVRD_IN,
> > +			     IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN);
> > +
> >  	return 0;
> >  }
> >
> > --
> > 2.34.1
> >