[PATCH v3 3/5] clk: samsung: clk-pll: Add support for pll_1061x

[Alim Akhtar]

Hi Alexandru

> -----Original Message-----
> From: Alexandru Chimac <alex at chimac.ro>
> Sent: Thursday, July 23, 2026 2:14 AM
> To: Krzysztof Kozlowski <krzk at kernel.org>; Sylwester Nawrocki
> <s.nawrocki at samsung.com>; Chanwoo Choi <cw00.choi at samsung.com>;
> Peter Griffin <peter.griffin at linaro.org>; Alim Akhtar
> <alim.akhtar at samsung.com>; Michael Turquette
> <mturquette at baylibre.com>; Stephen Boyd <sboyd at kernel.org>; Brian
> Masney <bmasney at redhat.com>; Rob Herring <robh at kernel.org>; Conor
> Dooley <conor+dt at kernel.org>; Alexandru Chimac <alex at chimac.ro>;
> Krzysztof Kozlowski <krzk+dt at kernel.org>
> Cc: linux-samsung-soc at vger.kernel.org; linux-clk at vger.kernel.org;
> devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org
> Subject: [PATCH v3 3/5] clk: samsung: clk-pll: Add support for pll_1061x
> 
> These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and are similar
> to pll_1460x (using CON3 instead of CON1), so the code for that can handle
> this PLL with a few small adaptations.
> 
It is good to mention that PLL_1061x is a fractional type PLL and used to supply BLK_MMC and AUD, atleast on 9610 SoC

> Signed-off-by: Alexandru Chimac <alex at chimac.ro>
> ---
>  drivers/clk/samsung/clk-pll.c | 29 ++++++++++++++++++++++-------
> drivers/clk/samsung/clk-pll.h |  1 +
>  2 files changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index
> e74552846ba3..2cda87235fa2 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -781,15 +781,20 @@ static unsigned long
> samsung_pll46xx_recalc_rate(struct clk_hw *hw,
>  	u64 fvco = parent_rate;
> 
>  	pll_con0 = readl_relaxed(pll->con_reg);
> -	pll_con1 = readl_relaxed(pll->con_reg + 4);
> -	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type ==
> pll_1460x) ?
> +	if (pll->type == pll_1061x)
> +		pll_con1 = readl_relaxed(pll->con_reg + 0xc);
Actually this is PLL_CON3 in UM, not suggesting to use a new variable but a comment here will help. 
Thanks!