[PATCH v4] PCI: imx6: Fix i.MX6Q/DL boot hang caused by improper PHY power sequencing

[Hongxing Zhu (OSS)]

> -----Original Message-----
> From: Bjorn Helgaas <helgaas at kernel.org>
> Sent: Tuesday, July 28, 2026 5:42 AM
> To: Hongxing Zhu (OSS) <hongxing.zhu at oss.nxp.com>
> Cc: Frank Li <frank.li at nxp.com>; l.stach at pengutronix.de; lpieralisi at kernel.org;
> kwilczynski at kernel.org; mani at kernel.org; robh at kernel.org;
> bhelgaas at google.com; s.hauer at pengutronix.de; kernel at pengutronix.de;
> festevam at gmail.com; linux-pci at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; imx at lists.linux.dev; linux-kernel at vger.kernel.org;
> Hongxing Zhu <hongxing.zhu at nxp.com>; Leonardo Costa
> <leoreis.costa at gmail.com>; Leonardo Costa <leonardo.costa at toradex.com>
> Subject: Re: [PATCH v4] PCI: imx6: Fix i.MX6Q/DL boot hang caused by improper
> PHY power sequencing
> 
> On Wed, Jul 22, 2026 at 03:10:30PM +0800, hongxing.zhu at oss.nxp.com wrote:
> > From: Richard Zhu <hongxing.zhu at nxp.com>
> >
> > Commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling
> > regulators") introduced a boot hang on i.MX6Q/DL variants by
> > reordering the initialization sequence, which exposed a critical PHY power
> control issue.
> >
> > Root cause:
> > Before commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling
> > regulators"), the sequence was:
> >   1. imx_pcie_assert_core_reset() - asserts TEST_PD, asserts REF_CLK_EN
> >   2. imx_pcie_clk_enable() - clears TEST_PD, asserts REF_CLK_EN
> >   3. Link training starts with TEST_PD properly cleared ✓
> >
> > After commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling
> > regulators"), the sequence became:
> >   1. imx_pcie_clk_enable() - clears TEST_PD, asserts REF_CLK_EN
> >   2. imx_pcie_assert_core_reset() - re-asserts TEST_PD, asserts REF_CLK_EN
> >   3. imx_pcie_deassert_core_reset() - does NOT clear TEST_PD
> >   4. Link training starts with TEST_PD still asserted ✗
> >
> > The reordering caused TEST_PD to be cleared prematurely in
> > clk_enable(), then re-asserted by assert_core_reset(), and never
> > cleared again before link training, resulting in the boot hang.
> 
> I intend to apply this patch for v7.2, but I have a separate question about why the
> link training failure causes a boot *hang*, not just a boot where we couldn't
> enumerate any PCIe devices.  It seems like the link training should time out, and
> we could emit a message (if
> desired) and continue without the PCIe controller.[] 
Before link training, the imx_setup_phy_mpll() function performs PHY
read/write operations for i.MX6Q/DL PCIe. These operations cause a boot hang
when the PHY is not powered up properly, which occurs before we even reach the
link training timeout mechanism.

Best Regards
Richard Zhu