[PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation

[Fuad Tabba]

Hi Sascha,

On Fri, 24 Jul 2026 at 11:54, Sascha Bischoff <Sascha.Bischoff at arm.com> wrote:
...

> +       case GICV5_IRS_IDR1:
> +               value = FIELD_PREP(GICV5_IRS_IDR1_PE_CNT,
> +                                  atomic_read(&vcpu->kvm->online_vcpus));
> +               /*
> +                * IRS_IDR1 encodes IAFFID_BITS as N - 1.
> +                */
> +               vpe_id_bits = vgic_v5_vmte_vpe_id_bits(vcpu);
> +               value |= FIELD_PREP(GICV5_IRS_IDR1_IAFFID_BITS, vpe_id_bits - 1);

I think the advertised IAFFID width might not cover the IAFFIDs KVM hands out.

vgic_v5_vmte_vpe_id_bits() sizes the VPE ID space from the vCPU count,
but the IAFFID a guest reads from ICC_IAFFIDR_EL1 is vcpu_id, which
userspace picks. Two vCPUs created with IDs 0 and 300 give an
IAFFID_BITS of one implemented bit, with the second vCPU reporting
300. I could not find anything in the spec requiring the reported
IAFFID to fit the advertised width, but to be sufficient to identify
every PE in the system if my read is correct.

Cheers,
/fuad