[PATCH] arm64: fix cpu-feature-registers Malformed table

[Randy Dunlap]

The "visible" column was dropped so that last line's extra pieces
should also be dropped to prevent a docs build error:

Documentation/arch/arm64/cpu-feature-registers.rst:170: ERROR: Malformed table.
Right border not aligned or missing.

+------------------------------+---------+
| Name                         |  bits   |
+------------------------------+---------+
| RNDR                         | [63-60] |
+------------------------------+---------+
| TS                           | [55-52] |
+------------------------------+---------+
...
+------------------------------+---------+
| AES                          | [7-4]   |
+------------------------------+---------+---------+ [docutils]

Fixes: bc7f7ddc64df ("arm64: Remove hidden bitfields from cpu-feature-registers.rst")
Signed-off-by: Randy Dunlap <rdunlap at infradead.org>
---
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will at kernel.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: Jonathan Corbet <corbet at lwn.net>
Cc: Shuah Khan <skhan at linuxfoundation.org>
Cc: linux-doc at vger.kernel.org
Cc: Mark Brown <broonie at kernel.org>

 Documentation/arch/arm64/cpu-feature-registers.rst |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-next-20260726.orig/Documentation/arch/arm64/cpu-feature-registers.rst
+++ linux-next-20260726/Documentation/arch/arm64/cpu-feature-registers.rst
@@ -167,7 +167,7 @@ infrastructure:
      | SHA1                         | [11-8]  |
      +------------------------------+---------+
      | AES                          | [7-4]   |
-     +------------------------------+---------+---------+
+     +------------------------------+---------+
 
 
   ID_AA64ISAR1_EL1 - Instruction set attribute register 1