[PATCH v7 18/19] dmaengine: ti: k3-udma-v2: Update glue layer to support PKTDMA V2
Sai Sree Kartheek Adivi
s-adivi at ti.com
Fri Jul 24 03:20:51 PDT 2026
Update glue layer to support PKTDMA V2 for non DMAengine users.
The updates include
- Handling absence of TISCI
- Direct IRQs
- Autopair: Lack of PSIL pair.
Signed-off-by: Sai Sree Kartheek Adivi <s-adivi at ti.com>
---
drivers/dma/ti/Kconfig | 2 +-
drivers/dma/ti/k3-udma-glue.c | 92 ++++++++++++++++++++++----------
drivers/dma/ti/k3-udma-private.c | 15 ++++++
drivers/dma/ti/k3-udma.h | 10 ++++
4 files changed, 90 insertions(+), 29 deletions(-)
diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig
index 40713bd1e8e9b..ada2ea8aca4b0 100644
--- a/drivers/dma/ti/Kconfig
+++ b/drivers/dma/ti/Kconfig
@@ -68,7 +68,7 @@ config TI_K3_UDMA_COMMON
config TI_K3_UDMA_GLUE_LAYER
tristate "Texas Instruments UDMA Glue layer for non DMAengine users"
depends on ARCH_K3 || COMPILE_TEST
- depends on TI_K3_UDMA
+ depends on TI_K3_UDMA || TI_K3_UDMA_V2
help
Say y here to support the K3 NAVSS DMA glue interface
If unsure, say N.
diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c
index bec4deb480e60..07952c4efee2d 100644
--- a/drivers/dma/ti/k3-udma-glue.c
+++ b/drivers/dma/ti/k3-udma-glue.c
@@ -267,6 +267,9 @@ static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm;
struct ti_sci_msg_rm_udmap_tx_ch_cfg req;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
@@ -525,21 +528,26 @@ int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn)
{
int ret;
- ret = xudma_navss_psil_pair(tx_chn->common.udmax,
- tx_chn->common.src_thread,
- tx_chn->common.dst_thread);
- if (ret) {
- dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (tx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ ret = xudma_navss_psil_pair(tx_chn->common.udmax,
+ tx_chn->common.src_thread,
+ tx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(tx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- tx_chn->psil_paired = true;
+ tx_chn->psil_paired = true;
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
- xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
+ } else {
+ xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+ }
k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en");
return 0;
@@ -705,7 +713,6 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
- req.nav_id = tisci_rm->tisci_dev_id;
req.index = rx_chn->udma_rchan_id;
req.rx_fetch_size = rx_chn->common.hdesc_size >> 2;
/*
@@ -725,11 +732,18 @@ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
req.rx_atype = rx_chn->common.atype_asel;
+ if (!tisci_rm->tisci) {
+ // TODO: look at the chan settings
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CFG_REG,
+ UDMA_CHAN_CFG_FILT_EINFO | UDMA_CHAN_CFG_FILT_PSWORDS);
+ return 0;
+ }
+
+ req.nav_id = tisci_rm->tisci_dev_id;
ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
if (ret)
dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n",
- rx_chn->udma_rchan_id, ret);
-
+ rx_chn->udma_rchan_id, ret);
return ret;
}
@@ -778,8 +792,11 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
}
if (xudma_is_pktdma(rx_chn->common.udmax)) {
- rx_ringfdq_id = flow->udma_rflow_id +
+ if (tisci_rm->tisci)
+ rx_ringfdq_id = flow->udma_rflow_id +
xudma_get_rflow_ring_offset(rx_chn->common.udmax);
+ else
+ rx_ringfdq_id = flow->udma_rflow_id;
rx_ring_id = 0;
} else {
rx_ring_id = flow_cfg->ring_rxq_id;
@@ -826,6 +843,14 @@ static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn,
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
}
+ if (!tisci_rm->tisci) {
+ xudma_rflowrt_write(flow->udma_rflow, UDMA_RX_FLOWRT_RFA,
+ UDMA_FLOWRT_RFA_RX_EINFO_PRESENT |
+ UDMA_FLOWRT_RFA_RX_PSINFO_PRESENT);
+ rx_chn->flows_ready++;
+ return 0;
+ }
+
memset(&req, 0, sizeof(req));
req.valid_params =
@@ -1330,6 +1355,9 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx);
rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq);
@@ -1371,6 +1399,9 @@ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
if (!rx_chn->remote)
return -EINVAL;
+ if (!tisci_rm->tisci)
+ return 0;
+
memset(&req, 0, sizeof(req));
req.valid_params =
TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID |
@@ -1406,21 +1437,26 @@ int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
if (rx_chn->flows_ready < rx_chn->flow_num)
return -EINVAL;
- ret = xudma_navss_psil_pair(rx_chn->common.udmax,
- rx_chn->common.src_thread,
- rx_chn->common.dst_thread);
- if (ret) {
- dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
- return ret;
- }
+ if (rx_chn->common.udmax->match_data->version == K3_UDMA_V1) {
+ ret = xudma_navss_psil_pair(rx_chn->common.udmax,
+ rx_chn->common.src_thread,
+ rx_chn->common.dst_thread);
+ if (ret) {
+ dev_err(rx_chn->common.dev, "PSI-L request err %d\n", ret);
+ return ret;
+ }
- rx_chn->psil_paired = true;
+ rx_chn->psil_paired = true;
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
- UDMA_CHAN_RT_CTL_EN);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_EN);
- xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
- UDMA_PEER_RT_EN_ENABLE);
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG,
+ UDMA_PEER_RT_EN_ENABLE);
+ } else {
+ xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG,
+ UDMA_CHAN_RT_CTL_AUTOPAIR | UDMA_CHAN_RT_CTL_EN);
+ }
k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en");
return 0;
diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-private.c
index 41299d3c3d91a..1eac4dcd5d880 100644
--- a/drivers/dma/ti/k3-udma-private.c
+++ b/drivers/dma/ti/k3-udma-private.c
@@ -3,6 +3,10 @@
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
* Author: Peter Ujfalusi <peter.ujfalusi at ti.com>
*/
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_platform.h>
@@ -165,6 +169,7 @@ void xudma_##res##rt_write(struct udma_##res *p, int reg, u32 val) \
EXPORT_SYMBOL(xudma_##res##rt_write)
XUDMA_RT_IO_FUNCTIONS(tchan);
XUDMA_RT_IO_FUNCTIONS(rchan);
+XUDMA_RT_IO_FUNCTIONS(rflow);
int xudma_is_pktdma(struct udma_dev *ud)
{
@@ -174,6 +179,11 @@ EXPORT_SYMBOL(xudma_is_pktdma);
int xudma_pktdma_tflow_get_irq(struct udma_dev *ud, int udma_tflow_id)
{
+ if (ud->match_data->version == K3_UDMA_V1) {
+ const struct udma_oes_offsets *oes = &ud->soc_data->oes;
+
+ return msi_get_virq(ud->dev, udma_tflow_id + oes->pktdma_tchan_flow);
+ }
struct platform_device *pdev = to_platform_device(ud->dev);
char irq_name[10];
@@ -184,6 +194,11 @@ EXPORT_SYMBOL(xudma_pktdma_tflow_get_irq);
int xudma_pktdma_rflow_get_irq(struct udma_dev *ud, int udma_rflow_id)
{
+ if (ud->match_data->version == K3_UDMA_V1) {
+ const struct udma_oes_offsets *oes = &ud->soc_data->oes;
+
+ return msi_get_virq(ud->dev, udma_rflow_id + oes->pktdma_rchan_flow);
+ }
struct platform_device *pdev = to_platform_device(ud->dev);
char irq_name[10];
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index fc8f0cfe7a36e..a2952183cd8e7 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -85,6 +85,14 @@
#define UDMA_CHAN_RT_CTL_PAIR_COMPLETE BIT(16)
#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
+/* UDMA_CHAN_CFG_REG */
+#define UDMA_CHAN_CFG_FILT_EINFO BIT(30)
+#define UDMA_CHAN_CFG_FILT_PSWORDS BIT(29)
+
+/* UDMA_RX_FLOWRT_RFA */
+#define UDMA_FLOWRT_RFA_RX_EINFO_PRESENT BIT(30)
+#define UDMA_FLOWRT_RFA_RX_PSINFO_PRESENT BIT(29)
+
/* UDMA_CHAN_RT_PDMA_STATE_REG */
#define UDMA_CHAN_RT_PDMA_STATE_IN_EVT BIT(31)
#define UDMA_CHAN_RT_PDMA_STATE_TDOWN BIT(30)
@@ -749,6 +757,8 @@ u32 xudma_rchanrt_read(struct udma_rchan *rchan, int reg);
void xudma_rchanrt_write(struct udma_rchan *rchan, int reg, u32 val);
bool xudma_rflow_is_gp(struct udma_dev *ud, int id);
int xudma_get_rflow_ring_offset(struct udma_dev *ud);
+u32 xudma_rflowrt_read(struct udma_rflow *rflow, int reg);
+void xudma_rflowrt_write(struct udma_rflow *rflow, int reg, u32 val);
int xudma_is_pktdma(struct udma_dev *ud);
--
2.54.0
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