[PATCH] clocksource/drivers/arm_arch_timer: Workaround bcm2712 broken EL2 virtual timer

[Jon Hunter]

On 23/07/2026 10:58, Marc Zyngier wrote:

...

>>>> I have posted something similar for Tegra [0], but because this is not
>>>> expected to work, I wanted to avoid the warnings here. We test for
>>>
>>> "not expected to work"? In which parallel universe is that a thing?
>>
>> FWIU, at least for Tegra194, we have a CPU and GIC pairing where the
>> CPU supports this but the GIC does not.
> 
> Oh please, you know better than this.
 >
> It isn't the GIC that defines the number of supported PPIs, it is the
> *integrator*. I.e. you. The GIC (GIC400 in this example) has full
> support for 16 PPIs per CPU.

Hmmm, I am looking at this spec [0] and it says ...

"The GIC-400 implements the interrupt types:
   16 Software Generated Interrupts (SGIs).
   6 external Private Peripheral Interrupts (PPIs) for each processor.
   1 internal PPI for each processor."

The table in [1] shows interrupts for non-sec, sec, virt and hypervisor 
timers, but I don't see a hyp-virt.

> I have a collection of VHE-capable machines with GIC400 that correctly
> implement the EL2 virtual timer PPI (if even Amlogic and AllWinner can
> get this right, really *anybody* can). My conclusion is that someone
> couldn't be bothered to drag a wire from one end to the other.

OK, so most likely I am still missing something here.

[0] 
https://developer.arm.com/documentation/ddi0471/b/introduction/about-the-gic-400?lang=en
[1] 
https://developer.arm.com/documentation/ddi0471/b/functional-description/interrupt-inputs-to-the-gic-400/ppis?lang=en

-- 
nvpublic