[PATCH v6 0/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5

[Robin Murphy]

On 2026-07-22 9:23 am, Will Deacon wrote:
> On Tue, 30 Jun 2026 14:01:16 +0100, Robin Murphy wrote:
>> v5: lore.kernel.org/r/20260603150025.30980-1-avivb at amazon.com
>>
>> Hi all,
>>
>> I'm reposting Aviv's series partly for visibility, since the previous
>> versions were buried in a thread, but also to respin patch #1 - Aviv had
>> fixed up the bugs in my initial draft, but I also get reports against the
>> original commit on my branch, so I ended up taking a second look, and
>> deciding the improvement was worthwhile.
>>
>> [...]
> 
> Applied to arm64 (for-next/perf), thanks!
> 
> [1/2] perf/arm-cmn: Move DTM index data out of hw_perf_event
>        https://git.kernel.org/arm64/c/56603c28d916
> [2/2] perf/arm-cmn: Add workarounds for CMN-S3 on Graviton5
>        https://git.kernel.org/arm64/c/9d0b1714e1af
> 
> If you get a chance, please can you take a look at Sashiko's comment on
> the second patch? It said something similar on Aviv's v5:
> 
>    https://sashiko.dev/#/patchset/cover.1782824005.git.robin.murphy@arm.com

I did already respond to that back on v3 or so - the code is correct 
compared to what the standard CMN tooling generates. The main DTC always 
has a logical ID of 0, while secondary DTCs inherit the logical ID of 
whatever XP they are attached to (and in this case the main DTC is on XP 
0 anyway so it works out neatly).

Subsequently I did also spend a while trying to make sense of the 
generation scripts themselves, and while I couldn't find any obvious 
proof that the DTC domain numbers (other than 0) will always line up 
with the logical ID order (although there definitely looks to be some 
sorting of things before the XP logical IDs are assigned), apparently 
it's not been an issue for anything anyone's built so far, and if it did 
become one, then it's a problem for arm_cmn_init_dtcs() to solve in general.

Cheers,
Robin.