[PATCH v5] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus

[Will Deacon]

On Mon, 08 Jun 2026 23:41:35 +0000, Besar Wicaksono wrote:
> The PMCCNTR_EL0 in NVIDIA Olympus CPU may increment while
> in WFI/WFE, which does not align with counting CPU_CYCLES
> on a programmable counter. Add a MIDR range entry and refuse
> PMCCNTR_EL0 for cycle events on affected parts so perf does
> not mix the two behaviors.
> 
> Also keep PMCCNTR_EL0 unavailable to EL0 direct counter reads
> on affected CPUs. When userspace counter access is enabled,
> avoid setting PMUSERENR_EL0.CR for PMUs that must avoid
> PMCCNTR_EL0, while still allowing direct reads from programmable
> event counters. For 64-bit userspace CPU_CYCLES events on PMUs
> without native long event counters, reject the event if the only
> valid direct-read path would be PMCCNTR_EL0.
> 
> [...]

Applied to arm64 (for-next/perf), thanks!

[1/1] perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus
      https://git.kernel.org/arm64/c/49f2413f9b55

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
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