[RFC PATCH 18/36] arm64: gicv3: remove GIC_PRIO_PSR_I_SET

[Jinjie Ruan]

On 7/9/2026 8:13 PM, Vladimir Murzin wrote:
> From: Ada Couprie Diaz <ada.coupriediaz at arm.com>
> 
> `GIC_PRIO_PSR_I_SET` was used to keep track of sections of the kernel
> where interrupts always need to reach the CPU and could not be masked

Did I miss something? I have not seen this usage of GIC_PRIO_PSR_I_SET.
In the kernel code I have observed, the use of GIC_PRIO_PSR_I_SET is
always because the interrupt has already been masked by the DAIF.I bit.

> via interrupt priorities, or DAIF bypassed the status of the PMR.
> 
> This flag unmasked IRQs when OR'd to GIC_PRIO_IRQOFF and ensured that

Did I miss something? I didn't see the code related to the OR'd to
GIC_PRIO_IRQOFF.

otherwise, LGTM
Reviewed-by: Jinjie Ruan <ruanjinjie at huawei.com>


> that IRQs were seen as disabled by the `local_irqs_...` functions,
> as they would only check the PMR if pseudo-NMIs were enabled.
> 
> This is not needed anymore as our IRQ masking APIs now know how to handle
> interrupt priorities properly and in parallel with DAIF : remove it.
> 
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz at arm.com>
> Signed-off-by: Vladimir Murzin <vladimir.murzin at arm.com>
> ---
>  arch/arm64/include/asm/ptrace.h         | 2 --
>  include/linux/irqchip/arm-gic-v3-prio.h | 8 --------
>  2 files changed, 10 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
> index 192eb97cd50b..c630165882e8 100644
> --- a/arch/arm64/include/asm/ptrace.h
> +++ b/arch/arm64/include/asm/ptrace.h
> @@ -24,8 +24,6 @@
>  #define GIC_PRIO_IRQON		GICV3_PRIO_UNMASKED
>  #define GIC_PRIO_IRQOFF		GICV3_PRIO_IRQ
>  
> -#define GIC_PRIO_PSR_I_SET	GICV3_PRIO_PSR_I_SET
> -
>  /* Additional SPSR bits not exposed in the UABI */
>  #define PSR_MODE_THREAD_BIT	(1 << 0)
>  #define PSR_IL_BIT		(1 << 20)
> diff --git a/include/linux/irqchip/arm-gic-v3-prio.h b/include/linux/irqchip/arm-gic-v3-prio.h
> index 44157c9abb78..464bf1d29453 100644
> --- a/include/linux/irqchip/arm-gic-v3-prio.h
> +++ b/include/linux/irqchip/arm-gic-v3-prio.h
> @@ -20,17 +20,11 @@
>   * GICV3_PRIO_NMI is the PMR view of the priority of pseudo-NMIs. This can be
>   * written to the PMR to mask pseudo-NMIs.
>   *
> - * On arm64 some code sections either automatically switch back to PSR.I or
> - * explicitly require to not use priority masking. If bit GICV3_PRIO_PSR_I_SET
> - * is included in the priority mask, it indicates that PSR.I should be set and
> - * interrupt disabling temporarily does not rely on IRQ priorities.
>   */
>  #define GICV3_PRIO_UNMASKED	0xe0
>  #define GICV3_PRIO_IRQ		0xc0
>  #define GICV3_PRIO_NMI		0x80
>  
> -#define GICV3_PRIO_PSR_I_SET	(1 << 4)
> -
>  #ifndef __ASSEMBLER__
>  
>  #define __gicv3_prio_to_ns(p)	(0xff & ((p) << 1))
> @@ -45,8 +39,6 @@ static_assert(__gicv3_prio_valid_ns(GICV3_PRIO_IRQ));
>  static_assert(GICV3_PRIO_NMI < GICV3_PRIO_IRQ);
>  static_assert(GICV3_PRIO_IRQ < GICV3_PRIO_UNMASKED);
>  
> -static_assert(GICV3_PRIO_IRQ < (GICV3_PRIO_IRQ | GICV3_PRIO_PSR_I_SET));
> -
>  #endif /* __ASSEMBLER */
>  
>  #endif /* __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H */