[PATCH] PCI: j721e: Fix incorrect max_lanes for J7200

[Manivannan Sadhasivam]

On Tue, 21 Jul 2026 10:57:43 -0500, Takuma Fujiwara wrote:
> The PCIe Controller in the J7200 SoC supports a 4-lane configuration.
> However, j7200_pcie_rc_data and j7200_pcie_ep_data incorrectly set
> .max_lanes = 2, limiting operation to fewer lanes than the hardware
> supports.
> 
> Set .max_lanes = 4 for both j7200_pcie_rc_data and j7200_pcie_ep_data to
> match the hardware capability.
> 
> [...]

Applied, thanks!

[1/1] PCI: j721e: Fix incorrect max_lanes for J7200
      commit: 7147a7bfce47acd48c3738130bf0bd692bfd80de

Best regards,
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