[PATCH v12 02/29] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state

Mark Brown broonie at kernel.org
Sun Jul 19 05:59:25 PDT 2026


On Sun, Jul 19, 2026 at 01:40:28PM +0100, Mark Brown wrote:
> On Sun, Jul 19, 2026 at 09:35:53AM +0100, Marc Zyngier wrote:

> > So leave this is a straight ISB, no optimisation. Once you come back
> > with actual data showing that this is a terrible bottleneck affecting
> > real workloads on real HW, we'll look at it. But until then, please
> > keep it as stupid as possible.

> I've already left the KVM hypervisor code like that - I only updated the
> code here in the main kernel since that keeps the end effect for
> existing systems and workloads the same.  I am aware that there has been
> a great deal of attention paid to the barriers we have in the context
> switch path so I am concerned that other people might have a different
> view on adding one.

It does also look odd do a conditional update of SMCR_EL1 and then
unconditionally add a barrier after it, even if the conditional
update suppressed the write.
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