[RFC PATCH 11/36] arm64: interrupts: introduce interrupt masking helpers for entry code

[Liao, Chang]

在 2026/7/14 23:45, Vladimir Murzin 写道:
> On 7/14/26 08:33, Liao, Chang wrote:
>> 在 2026/7/9 20:13, Vladimir Murzin 写道:
>>> diff --git a/arch/arm64/include/asm/interrupts/entry.h b/arch/arm64/include/asm/interrupts/entry.h
>>> new file mode 100644
>>> index 000000000000..3034c490ed66
>>> --- /dev/null
>>> +++ b/arch/arm64/include/asm/interrupts/entry.h
>>> @@ -0,0 +1,110 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>> +/*
>>> + * Copyright (C) 2025 Arm Ltd.
>>> + */
>>> +#ifndef __ASM_INTERRUPTS_ENTRY_H
>>> +#define __ASM_INTERRUPTS_ENTRY_H
>>> +
>>> +#include <asm/arch_gicv3.h>
>>> +#include <asm/bug.h>
>>> +#include <asm/cpufeature.h>
>>> +#include <asm/interrupts/common_flags.h>
>>> +
>>> +
>>> +static __always_inline
>>> +arm64_exc_hwstate_t __arm64_switch_exc_hwstate_to(arm64_exc_hwstate_t prev,
>>> +						  arm64_exc_hwstate_t next)
>>> +{
>>> +	bool update_pmr = system_uses_irq_prio_masking() && prev.pmr != next.pmr;
>>> +
>>> +	arm64_debug_exc_hwstate(prev);
>>> +
>>> +	if (prev.flags == next.flags)
>>> +		return next;
>>> +
>>> +	if (!arch_irqs_disabled_flags(next.flags))
>>> +		trace_hardirqs_on();
>>> +
>>> +	arm64_update_exc_hwstate(next, update_pmr);
>>> +
>>> +	if (arch_irqs_disabled_flags(next.flags))
>>> +		trace_hardirqs_off();
>>> +
>>> +	return next;
>>> +}
>>> +
>>> +static __always_inline
>>> +arm64_exc_hwstate_t arm64_inherit_exc_context(struct pt_regs *regs)
>>> +{
>>> +	arm64_exc_hwstate_t prev = arm64_exc_hwstate_of_context(CRITICAL_CONTEXT);
>>> +	arm64_exc_hwstate_t next = arm64_inherit_exc_hwstate(regs);
>>> +
>>> +	return __arm64_switch_exc_hwstate_to(prev, next);
>>> +}
>>> +
>>> +static __always_inline
>>> +arm64_exc_hwstate_t arm64_drop_exc_context(arm64_exc_hwstate_t prev, arm64_exc_context_t context)
>>> +{
>>> +	arm64_exc_hwstate_t next = arm64_exc_hwstate_of_context(context);
>>> +
>>> +	if (IS_ENABLED(CONFIG_DEBUG_IRQFLAGS)) {
>>> +		bool pnmi = system_uses_irq_prio_masking();
>>> +
>>> +		WARN_ON_ONCE(context > ERROR_CONTEXT &&
>>> +			     prev.daif == DAIF_ERRCTX);
>> By definition, arm64_drop_exc_context() seems to require the target context to mask fewer (or equal)
>> exception types than the prev state. In this case, if context > ERROR_CONTEXT while
>> prev.daif == DAIF_PROCCTX_NOIRQ, doesn't that violate this assumption?
>>
> 
> My AI disagrees with your AI :D Honestly, prev.daif == DAIF_PROCCTX_NOIRQ is few lines bellow and
> we guard it with context > NONMI_CONTEXT which covers ERROR_CONTEXT and CRITICAL_CONTEXT as well.

Ah, sorry for the nosie, I completely overlooked the additional guard checks a few lines beblow,
thanks for pointing out. Your AI wins this round.

> 
>>> +
>>> +		WARN_ON_ONCE(context > NONMI_CONTEXT &&
>>> +			     prev.daif == DAIF_PROCCTX_NOIRQ);
>>> +
>>> +		WARN_ON_ONCE(context > NOIRQ_CONTEXT &&
>>> +			     pnmi && prev.pmr == GIC_PRIO_IRQOFF);
>>> +
>>> +		WARN_ON_ONCE(context > PROCESS_CONTEXT &&
>>> +			     ((pnmi && prev.daif == DAIF_PROCCTX && prev.pmr == GIC_PRIO_IRQON) ||
>>> +			      (!pnmi && prev.daif == DAIF_PROCCTX)));
>>> +	}
>>> +
>>> +	return __arm64_switch_exc_hwstate_to(prev, next);
>>> +}
>>> +
>>> +static __always_inline
>>> +arm64_exc_hwstate_t arm64_lift_exc_context(arm64_exc_hwstate_t prev, arm64_exc_context_t context)
>>> +{
>>> +	arm64_exc_hwstate_t next = arm64_exc_hwstate_of_context(context);
>>> +
>>> +	if (IS_ENABLED(CONFIG_DEBUG_IRQFLAGS)) {
>>> +		bool pnmi = system_uses_irq_prio_masking();
>>> +
>>> +		WARN_ON_ONCE(context < CRITICAL_CONTEXT &&
>>> +			     prev.daif == DAIF_MASK);
>> Is it intentional to allow prev.daif == DAIF_ERRCTX when context has a value of NONMI_CONTEXT,
>> NOIRQ_CONTEXT or PROCESS_CONTEXT? Or should these transitions also be caught here?
>>
>> By definition, arm64_lift_exc_context() seems to require the target context to mask more (or equal)
>> exception types than the prev state. Allowing these transitions appears to violate that assumption.
>>
> 
> Similarly prev.daif == DAIF_ERRCTX is few lines bellow and it is guarded by context < ERROR_CONTEXT
> which covers NONMI_CONTEXT, NOIRQ_CONTEXT and PROCESS_CONTEXT.

Thanks for pointing out.

> 
>>> +
>>> +		WARN_ON_ONCE(context < ERROR_CONTEXT &&
>>> +			     prev.daif == DAIF_ERRCTX);
>>> +
>>> +		WARN_ON_ONCE(context < NONMI_CONTEXT &&
>>> +			     pnmi && prev.daif == DAIF_PROCCTX_NOIRQ);
>>> +
>>> +		WARN_ON_ONCE(context < NOIRQ_CONTEXT &&
>>> +			     ((pnmi && prev.pmr == GIC_PRIO_IRQOFF) ||
>>> +			      (!pnmi && prev.daif == DAIF_PROCCTX_NOIRQ)));
>>> +	}
>>> +
>>> +	return __arm64_switch_exc_hwstate_to(prev, next);
>>> +}
>>> +
>>> +
>>> +static __always_inline
>>> +arm64_exc_hwstate_t arm64_unmask_exc_context(arm64_exc_context_t context)
>>> +{
>>> +	arm64_exc_hwstate_t prev = arm64_exc_hwstate_of_context(CRITICAL_CONTEXT);
>>> +
>>> +	return arm64_drop_exc_context(prev, context);
>>> +}
>>> +
>>> +static __always_inline
>>> +arm64_exc_hwstate_t arm64_mask_exc_context(arm64_exc_hwstate_t prev)
>>> +{
>>> +	return arm64_lift_exc_context(prev, CRITICAL_CONTEXT);
>>> +}
>>> +
>>> +#endif /* __ASM_INTERRUPTS_ENTRY_H */
>>
>> -- BR Liao, Chang
>>
> 
> Cheers
> Vladimir
> 


-- 
BR
Liao, Chang