[PATCH v3 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation

[Nicolin Chen]

On Tue, Jul 14, 2026 at 03:46:07PM -0300, Jason Gunthorpe wrote:
> +static unsigned int arm_smmu_compute_ttl(u8 leaf_bitmap, u8 table_bitmap,
> +	} else {
> +		/* Both bitmaps zero is not allowed */
> +		return 0;
> +	}

"not allowed" reads like we need a WARN_ON?

Otherwise, should it be reworded?

> +static u8 arm_smmu_tlbi_calc_stride(struct arm_smmu_tlbi *tlbi)
> +{
> +	u8 combined = tlbi->table_levels_bitmap | tlbi->leaf_levels_bitmap;
> +	u8 tg_szlg2 = tlbi->tgsz_lg2;
> +
> +	if (!combined)
> +		return U8_MAX;

As the code checks "combined", ...

> +	 * If leaf_levels_bitmap is 0 then this is a walk cache only
> +	 * invalidation. If table_levels_bitmap is 0 then this is a leaf only
> +	 * invalidation.

..., how about listing all combinations in this kdocs:
       * The pair (table, leaf) below selects the invalidation scope:
       *   table!=0, leaf==0 : walk cache only
       *   table==0, leaf!=0 : leaves only
       *   table!=0, leaf!=0 : walk cache + leaves
       *   table==0, leaf==0 : a full invalidation
?

> +	 * Level bitmaps use iommupt numbering: bit 0 is the leaf-only level
> +	 * (ARM level 3), bit 1 is the next level up (ARM level 2), etc.

Also, the driver calculates ttl via the inverted numbering noted
here. How about:

static inline int arm_smmu_bitmap_to_level(u8 bitmap)
{
      return 3 - (int)__ffs(bitmap);
}

?

Then, arm_smmu_compute_ttl() would read slightly better.

With that,

Reviewed-by: Nicolin Chen <nicolinc at nvidia.com>