[RFC PATCH 08/36] irqchip/gic-v3: make the unmasking of pseudo-NMIs explicit when handling IRQs

[Jinjie Ruan]

On 7/9/2026 8:13 PM, Vladimir Murzin wrote:
> From: Ada Couprie Diaz <ada.coupriediaz at arm.com>
> 
> `gic_arch_enable_irqs()` is only used when handling IRQs (which could
> be pseudo-NMIs) and unmasking pseudo-NMIs.
> 
> The chain of `gic_pmr_mask_irqs()` and `gic_arch_enable_irqs()` for it
> is slightly confusing without further explanation.
> 
> Remove `gic_arch_enable_irqs()` and instead do the whole pseudo-NMI
> umasking in `gic_unmask_pnmis()`, making the operation explicit.
> 
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz at arm.com>
> Signed-off-by: Vladimir Murzin <vladimir.murzin at arm.com>
> ---
>  arch/arm/include/asm/arch_gicv3.h     | 6 +-----
>  arch/arm64/include/asm/arch_gicv3.h   | 7 +++++--
>  arch/arm64/include/asm/entry-common.h | 2 +-
>  drivers/irqchip/irq-gic-v3.c          | 5 +----
>  4 files changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
> index 847590df7551..d4ac8d3271b1 100644
> --- a/arch/arm/include/asm/arch_gicv3.h
> +++ b/arch/arm/include/asm/arch_gicv3.h
> @@ -246,11 +246,7 @@ static inline void gic_pmr_mask_irqs(void)
>  	WARN_ON_ONCE(true);
>  }
>  
> -static inline void gic_arch_enable_irqs(void)
> -{
> -	/* Should not get called. */
> -	WARN_ON_ONCE(true);
> -}
> +static inline void gic_unmask_pnmis(void) {}
>  
>  static inline bool gic_has_relaxed_pmr_sync(void)
>  {
> diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
> index d20b03931a8d..3dcb7b8309d9 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -178,9 +178,12 @@ static inline void gic_pmr_mask_irqs(void)
>  	gic_write_pmr(GIC_PRIO_IRQOFF);
>  }
>  
> -static inline void gic_arch_enable_irqs(void)
> +static inline void gic_unmask_pnmis(void)
>  {
> -	asm volatile ("msr daifclr, #3" : : : "memory");
> +	if (gic_prio_masking_enabled()) {
> +		gic_pmr_mask_irqs();
> +		asm volatile ("msr daifclr, #3" : : : "memory");
> +	}

LGTM
Reviewed-by: Jinjie Ruan <ruanjinjie at huawei.com>

>  }
>  
>  static inline bool gic_has_relaxed_pmr_sync(void)
> diff --git a/arch/arm64/include/asm/entry-common.h b/arch/arm64/include/asm/entry-common.h
> index cab8cd78f693..1905765159aa 100644
> --- a/arch/arm64/include/asm/entry-common.h
> +++ b/arch/arm64/include/asm/entry-common.h
> @@ -32,7 +32,7 @@ static inline bool arch_irqentry_exit_need_resched(void)
>  	/*
>  	 * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
>  	 * priority masking is used the GIC irqchip driver will clear DAIF.IF
> -	 * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
> +	 * in gic_unmask_pnmis() for normal IRQs. If anything is set in
>  	 * DAIF we must have handled an NMI, so skip preemption.
>  	 */
>  	if (system_uses_irq_prio_masking() && read_sysreg(daif))
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 99444a1b2ffa..94c6a3f2b009 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -867,10 +867,7 @@ static void __gic_handle_irq_from_irqson(struct pt_regs *regs)
>  		nmi_exit();
>  	}
>  
> -	if (gic_prio_masking_enabled()) {
> -		gic_pmr_mask_irqs();
> -		gic_arch_enable_irqs();
> -	}
> +	gic_unmask_pnmis();
>  
>  	if (!is_nmi)
>  		__gic_handle_irq(irqnr, regs);