[PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE

[Nicolin Chen]

On Mon, Jul 06, 2026 at 01:26:45PM -0300, Jason Gunthorpe wrote:
> If DS is supported then SCALE can go up to 39. Detect the IDR and compute
> a scale max that is compatible for the entire invs list.
> 
> Signed-off-by: Jason Gunthorpe <jgg at nvidia.com>

Reviewed-by: Nicolin Chen <nicolinc at nvidia.com>

> @@ -5235,6 +5242,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
>  	/* Maximum number of outstanding stalls */
>  	smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg);
>  
> +	if (reg & IDR5_DS)
> +		smmu->features |= ARM_SMMU_FEAT_DS;
> +

Just a note here:

This somehow conflicts with my iommufd_invalidation_loop series
where we sanitize user space commands, because the driver would
support IDR5.DS. So, one of the series would need a rebase.

Nicolin