[PATCH v3 3/6] arm64: dts: qcom: kodiak: Add GEM_NOC interconnect for adreno SMMU

[Bibek Kumar Patro]

On 7/6/2026 11:12 PM, Dmitry Baryshkov wrote:
> On Mon, Jul 06, 2026 at 10:26:36PM +0530, Bibek Kumar Patro wrote:
>> On Kodiak platforms, the Adreno SMMU requires a bandwidth vote on
>> the GEM_NOC path (MASTER_GPU_TCU -> SLAVE_EBI1) before its registers
>> are accessible. Without this vote, the SMMU may become unreachable,
>> leading to intermittent probe failures and runtime issues.
>>
>> Add the required interconnect to ensure reliable register access.
>>
>> Signed-off-by: Bibek Kumar Patro <bibek.patro at oss.qualcomm.com>
>> ---
>>   arch/arm64/boot/dts/qcom/kodiak.dtsi | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> index 90e50c245c0c..721526f023dd 100644
>> --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
>> @@ -3389,6 +3389,8 @@ adreno_smmu: iommu at 3da0000 {
>>   
>>   			power-domains = <&gpucc GPU_CC_CX_GDSC>;
>>   			dma-coherent;
>> +			interconnects = <&gem_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> 
> Why is it ALWAYS? Would it be better to declare it as ACTIVE_ONLY and

Added QCOM_ICC_TAG_ALWAYS, to hold the vote in SLEEP bucket as well
preventing gem_noc going to sleep when icc_set_bw is being called.

> then drop the extra suspend/resume play?

Not sure if I understood it correctly.
Did you mean the extra suspend/resume play in arm_smmu_runtime_suspend
or in arm_smmu_device_shutdown() path?

Thanks & regards,
Bibek

> 
>>   		};
>>   
>>   		gfx_0_tbu: tbu at 3dd9000 {
>>
>> -- 
>> 2.34.1
>>
>